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<title>Sample Waveforms for lpm_fifo_dc0.tdf </title>
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<h2><CENTER>Sample behavioral waveforms for design file lpm_fifo_dc0.tdf </CENTER></h2>
<P>The following waveforms show the behavior of scfifo megafunction for the chosen set of parameters in design lpm_fifo_dc0.tdf. The design lpm_fifo_dc0.tdf has a depth of 8 words of 8 bits each. The output of the fifo is unregistered. The fifo is in show-ahead synchronous mode. The data becomes available before 'rdreq' is asserted; 'rdreq' acts as a read acknowledge. </P>
<CENTER><img src=lpm_fifo_dc0_wave0.jpg> </CENTER>
<P><CENTER><FONT size=2>Fig. 1 : Wave showing read and write operation. </CENTER></P>
<P><FONT size=3>The above waveform shows the behavior of the design under normal read and write conditions . </P>
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简单的UART--verilog
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2010-07-19
10:04:47
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收藏 876KB RAR 举报 
uart.rar （92个子文件） 
mod 
vsim.wlf 40KB uart_ctrl.v 14KB work txd_ctrl _primary.vhd 498B _primary.dat 3KB rxd_ctrl _primary.vhd 584B _primary.dat 4KB uart_ctrl _primary.vhd 777B _primary.dat 931B _opt work__info 1000B work_rxd_ctrl_fast.asm 27KB work_txd_ctrl_fast.dt2 256B work_uart_ctrl_fast.asm 5KB work_uart_ctrl_fast.dt2 452B work_txd_ctrl_fast.asm 20KB work_rxd_ctrl_fast.dt2 256B work_uart_ctrl_tb_fast.asm 11KB _deps 394B work_uart_ctrl_tb_fast.dt2 364B _temp uart_ctrl_tb _primary.vhd 84B _primary.dat 1KB _info 1000B wave.do 4KB uart.mpf 30KB uart_ctrl_tb.v 1KB uart.cr.mti 519B modelsim.ini 28KB uart_ctrl.xml 1008B uart_ctrl_par.v 1KB quartur altpll0.tdf 12KB uart.pof 2MB uart.qsf 20KB lpm_fifo_dc0.cmp 1KB uart.fit.rpt 291KB uart.jdi 4KB stp1.stp 219KB altpll0.ppf 355B test.bsf 4KB uart.qws 843B uart.map.summary 464B
lpm_fifo_dc0_waveforms.html 837B uart.pin 77KB
altpll0_wave0.jpg 402KB uart.fit.summary 606B incremental_db compiled_partitions uart.sldhu_30e344a040fd07e1533c49de5f2d67d1.map.hdbx 9KB uart.sldhu_30e344a040fd07e1533c49de5f2d67d1.map.logdb 4B uart.root_partition.cmp.hdbx 16KB uart.root_partition.map.kpt 76KB uart.autos_3e92b2e5d298f5cf757a393f7655ccd81.map.atm 167KB uart.sldhu_30e344a040fd07e1533c49de5f2d67d1.map.kpt 39KB uart.root_partition.map.dpi 5KB uart.root_partition.merge_hb.atm 63KB uart.root_partition.cmp.dfp 33B uart.root_partition.cmp.kpt 341B uart.autos_3e92b2e5d298f5cf757a393f7655ccd81.map.logdb 4B uart.sldhu_30e344a040fd07e1533c49de5f2d67d1.map.dpi 1KB uart.sldhu_30e344a040fd07e1533c49de5f2d67d1.map.atm 21KB uart.root_partition.map.hdbx 16KB uart.root_partition.cmp.logdb 4B uart.root_partition.cmp.atm 57KB uart.root_partition.map.atm 45KB uart.root_partition.cmp.rcf 89KB uart.autos_3e92b2e5d298f5cf757a393f7655ccd81.map.hdbx 38KB uart.autos_3e92b2e5d298f5cf757a393f7655ccd81.map.kpt 574KB README 653B uart.qpf 903B uart.tan.summary 3KB uart.tan.rpt 1.02MB uart_ctrl.v.bak 14KB lpm_fifo_dc0_wave0.jpg 70KB test.v 3KB lpm_fifo_dc0_wave1.jpg 90KB uart_ctrl.v 14KB uart.sof 821KB uart.map.rpt 208KB txd_ctrl.bsf 3KB uart.bdf 17KB uart_ctrl.bsf 4KB uart.map.smsg 85B altpll0_waveforms.html 628B uart.done 26B lpm_fifo_dc0.tdf 6KB test.v.bak 3KB uart.flow.rpt 22KB altpll0.bsf 3KB lpm_fifo_dc0.bsf 3KB uart.fit.smsg 513B rxd_ctrl.bsf 3KB altpll0.qip 446B lpm_fifo_dc0.qip 378B uart.asm.rpt 7KB uart_ctrl_par.v 938B altpll0.cmp 907B资源评论
linsz0222013-03-01这个比较不错，有完整的工程- cqupt_c2012-08-14完整的工程，很好，值得参考
blalbl2013-03-28做得还行，就是我自己知道怎么下手~
