verilog-uart-master.zip （65个子文件） 
verilog-uart-master 
.travis.yml 443B example NexysVideo fpga fpga.xdc 2KB rtl sync_reset.v 2KB debounce_switch.v 3KB fpga_core.v 3KB fpga.v 4KB sync_signal.v 2KB common vivado.mk 4KB lib uart 12B Makefile 402B fpga Makefile 509B ML605 fpga rtl sync_reset.v 2KB debounce_switch.v 3KB fpga_core.v 4KB fpga.v 6KB sync_signal.v 2KB common xilinx.mk 6KB lib uart 12B Makefile 402B fpga.ucf 6KB fpga Makefile 905B ATLYS fpga rtl sync_reset.v 2KB debounce_switch.v 3KB fpga_core.v 4KB fpga.v 4KB sync_signal.v 2KB common xilinx.mk 6KB lib uart 12B Makefile 402B fpga.ucf 12KB fpga Makefile 750B VCU108 fpga fpga.xdc 3KB rtl sync_reset.v 2KB debounce_switch.v 3KB fpga_core.v 3KB fpga.v 5KB sync_signal.v 2KB common vivado.mk 4KB lib uart 12B Makefile 402B fpga Makefile 965B Arty fpga fpga.xdc 4KB rtl sync_reset.v 2KB debounce_switch.v 3KB fpga_core.v 4KB fpga.v 5KB sync_signal.v 2KB common vivado.mk 4KB lib uart 12B Makefile 402B fpga Makefile 951B tb test_uart_tx.py 4KB uart_ep.py 5KB test_uart_rx.py 4KB axis_ep.py 17KB test_uart_tx.v 2KB test_uart_rx.v 2KB rtl uart.v 3KB uart_rx.v 4KB uart_tx.v 3KB README 9B AUTHORS 40B .gitignore 33B README.md 4KB COPYING 1KB资源评论
