vhdl实现交通灯课程设计作业

library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all; entity seven_seg is port ( clk : in std_logic; dig_sel_n : out std_logic_vector(7 downto 0);----------位选信号(哪几个数码管亮) data_out : out std_logic_vector(7 downto 0)-----------段选信号(每个数码管中显示0-9哪个数) ); end entity seven_seg; architecture bhv of seven_seg is signal dig0, dig1, dig2, dig3 : std_logic_vector(7 downto 0);-----dig0,1,2,3包含的就是数码管0,1,2,3显示的内容 signal digSelectAddress: integer range 0 to 3;--------------------当前将要显示数码管的地址控制线,用到了四位 signal clock_3ms: std_logic;--------------------------------------clock_3ms => 3ms 显示刷新脉冲信号线； --------------------数码管的译码函数----------------------------------------- ----- 形参 data :为要译码的数字，范围为：0－－9； ----- 返回值 ledSegment :为译码好的七段数码管段码； function decode( data: integer range 0 to 9 ) return std_logic_vector is variable ledSegment: std_logic_vector(7 downto 0); begin CASE data IS WHEN 0 => ledSegment := "11000000";-- 0xC0;0 WHEN 1 => ledSegment := "11111001";-- 0xf9;1 WHEN 2 => ledSegment := "10100100";-- 0xa4;2 WHEN 3 => ledSegment := "10110000";-- 0xb0;3 WHEN 4 => ledSegment := "10011001";-- 0x99;4 WHEN 5 => ledSegment := "10010010";-- 0x92;5 WHEN 6 => ledSegment := "10000010";-- ox82;6 WHEN 7 => ledSegment := "11111000";-- 0xf8;7 WHEN 8 => ledSegment := "10000000";-- 0x80;8 WHEN 9 => ledSegment := "10010000";-- 0x90;9 WHEN OTHERS => null; END CASE; return ledSegment; end decode; begin dig3 <= decode(1);------------------------第四个数码管显示1 dig2 <= decode(2);------------------------第三个数码管显示2 dig1 <= decode(3);------------------------第二个数码管显示3 dig0 <= decode(4);------------------------第一个数码管显示4 -------------------------------------------------------------------------------------------------------------- Div_clock_3ms: process(clk)--------------clock_3ms => 3ms 数码管显示刷新脉冲信号 variable count :integer range 0 to 30_000 ; begin if(clk = '1' and clk'event) then if count = 29_999 then count:= 0; else count:= count + 1; end if; if(count>= 15_000) then clock_3ms <= '0'; else clock_3ms <= '1'; end if; end if; end process Div_clock_3ms; -------------------------------------------------------------------------------------------------------------- counter: process(clock_3ms)-----------------------因为只有八位数据线每次只能送8位数（一个数码管的显示内容），因此每3ms后移一个数码管显示，利用人眼的惰性，实现动态刷新 begin if(clock_3ms = '1' and clock_3ms'event) then if digSelectAddress = 3 then digSelectAddress <= 0; else digSelectAddress <= digSelectAddress + 1;---------加1后移一位 end if; end if; end process counter; -------------------------------------------------------------------------------------------------------------- show: process(digSelectAddress) begin case digSelectAddress is-------------位选信号digSelectAddress 低电平有效 when 0 => dig_sel_n <= "11111110";data_out <= dig0; when 1 => dig_sel_n <= "11111101";data_out <= dig1;------当地址选通信号为1，位选dig_sel_n8位得出，显示的内容data_out显示对应的dig when 2 => dig_sel_n <= "11111011";data_out <= dig2; when 3 => dig_sel_n <= "11110111";data_out <= dig3; WHEN OTHERS => null; end case; end process; end architecture bhv;