################################################################################
# Vivado (TM) v2020.2 (64-bit)
#
# README.txt: Please read the sections below to understand the steps required
# to simulate the design for a simulator, the directory structure
# and the generated exported files.
#
################################################################################
1. Simulate Design
To simulate design, cd to the simulator directory and execute the script.
For example:-
% cd questa
% ./top.sh
The export simulation flow requires the Xilinx pre-compiled simulation library
components for the target simulator. These components are referred using the
'-lib_map_path' switch. If this switch is specified, then the export simulation
will automatically set this library path in the generated script and update,
copy the simulator setup file(s) in the exported directory.
If '-lib_map_path' is not specified, then the pre-compiled simulation library
information will not be included in the exported scripts and that may cause
simulation errors when running this script. Alternatively, you can provide the
library information using this switch while executing the generated script.
For example:-
% ./top.sh -lib_map_path /design/questa/clibs
Please refer to the generated script header 'Prerequisite' section for more details.
2. Directory Structure
By default, if the -directory switch is not specified, export_simulation will
create the following directory structure:-
<current_working_directory>/export_sim/<simulator>
For example, if the current working directory is /tmp/test, export_simulation
will create the following directory path:-
/tmp/test/export_sim/questa
If -directory switch is specified, export_simulation will create a simulator
sub-directory under the specified directory path.
For example, 'export_simulation -directory /tmp/test/my_test_area/func_sim'
command will create the following directory:-
/tmp/test/my_test_area/func_sim/questa
By default, if -simulator is not specified, export_simulation will create a
simulator sub-directory for each simulator and export the files for each simulator
in this sub-directory respectively.
IMPORTANT: Please note that the simulation library path must be specified manually
in the generated script for the respective simulator. Please refer to the generated
script header 'Prerequisite' section for more details.
3. Exported script and files
Export simulation will create the driver shell script, setup files and copy the
design sources in the output directory path.
By default, when the -script_name switch is not specified, export_simulation will
create the following script name:-
<simulation_top>.sh (Unix)
When exporting the files for an IP using the -of_objects switch, export_simulation
will create the following script name:-
<ip-name>.sh (Unix)
Export simulation will create the setup files for the target simulator specified
with the -simulator switch.
For example, if the target simulator is "ies", export_simulation will create the
'cds.lib', 'hdl.var' and design library diectories and mappings in the 'cds.lib'
file.
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Vivado 下 IP核之双端口 RAM 读写
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Vivado 下 IP核之双端口 RAM 读写 双端口 RAM 是指拥有两个读写端口的 RAM,有伪双端口 RAM(一个端口只能读,另一个端口只能写)和真双端口 RAM(两个端口都可以进行读写操作)之分。一般当我们需要同时对存储器进行读写操作时会使用到双端口 RAM,例如有一个 FIFO 存储器,我们需要同时对其进行数据的写入和读出,这时候就需要一个写端口和一个读端口了。
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Vivado 下 IP核之双端口 RAM 读写 (312个子文件)
__synthesis_is_complete__ 0B
__synthesis_is_complete__ 0B
xsim.ini.bak 30KB
elaborate.bat 1KB
simulate.bat 975B
compile.bat 899B
runme.bat 229B
runme.bat 229B
xsim_1.c 10KB
xsim.dbg 78KB
ila_0.dcp 624KB
ila_0.dcp 624KB
ila_0.dcp 622KB
blk_mem_gen_0.dcp 29KB
blk_mem_gen_0.dcp 29KB
blk_mem_gen_0.dcp 29KB
compile.do 750B
compile.do 736B
compile.do 716B
compile.do 712B
compile.do 680B
compile.do 678B
compile.do 670B
compile.do 664B
simulate.do 334B
simulate.do 333B
simulate.do 333B
simulate.do 296B
simulate.do 287B
simulate.do 287B
elaborate.do 213B
simulate.do 196B
simulate.do 180B
elaborate.do 175B
wave.do 32B
wave.do 32B
wave.do 32B
wave.do 32B
wave.do 32B
wave.do 32B
wave.do 32B
wave.do 32B
simulate.do 11B
simulate.do 11B
xsimk.exe 109KB
run.f 505B
run.f 485B
run.f 448B
run.f 432B
usage_statistics_ext_xsim.html 3KB
.xsim_webtallk.info 64B
xsim.ini 30KB
xsim.ini 29KB
xsim.ini 29KB
xsimSettings.ini 1KB
webtalk.jou 985B
webtalk_18904.backup.jou 985B
vivado.jou 828B
vivado.jou 800B
vivado.jou 772B
ISEWrap.js 8KB
ISEWrap.js 8KB
rundef.js 1KB
rundef.js 1KB
runme.log 33KB
runme.log 20KB
elaborate.log 2KB
xvlog.log 1KB
compile.log 1KB
webtalk.log 1KB
webtalk_18904.backup.log 1KB
vivado.log 1KB
summary.log 979B
summary.log 979B
summary.log 979B
summary.log 979B
summary.log 979B
summary.log 979B
summary.log 979B
summary.log 979B
summary.log 979B
summary.log 979B
simulate.log 506B
xsimkernel.log 335B
xsimcrash.log 0B
ip_2port_ram.lpr 290B
xsim.mem 14KB
xsim_0.win64.obj 53KB
xsim_1.win64.obj 6KB
elab.opt 218B
elab.opt 180B
vivado.pb 53KB
vivado.pb 32KB
xelab.pb 4KB
xvlog.pb 2KB
ila_0_utilization_synth.pb 276B
blk_mem_gen_0_utilization_synth.pb 276B
tb_ip_2port_ram_vlog.prj 567B
vlog.prj 208B
vlog.prj 153B
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