################################################################################
# Vivado (TM) v2020.2 (64-bit)
#
# README.txt: Please read the sections below to understand the steps required
# to simulate the design for a simulator, the directory structure
# and the generated exported files.
#
################################################################################
1. Simulate Design
To simulate design, cd to the simulator directory and execute the script.
For example:-
% cd questa
% ./top.sh
The export simulation flow requires the Xilinx pre-compiled simulation library
components for the target simulator. These components are referred using the
'-lib_map_path' switch. If this switch is specified, then the export simulation
will automatically set this library path in the generated script and update,
copy the simulator setup file(s) in the exported directory.
If '-lib_map_path' is not specified, then the pre-compiled simulation library
information will not be included in the exported scripts and that may cause
simulation errors when running this script. Alternatively, you can provide the
library information using this switch while executing the generated script.
For example:-
% ./top.sh -lib_map_path /design/questa/clibs
Please refer to the generated script header 'Prerequisite' section for more details.
2. Directory Structure
By default, if the -directory switch is not specified, export_simulation will
create the following directory structure:-
<current_working_directory>/export_sim/<simulator>
For example, if the current working directory is /tmp/test, export_simulation
will create the following directory path:-
/tmp/test/export_sim/questa
If -directory switch is specified, export_simulation will create a simulator
sub-directory under the specified directory path.
For example, 'export_simulation -directory /tmp/test/my_test_area/func_sim'
command will create the following directory:-
/tmp/test/my_test_area/func_sim/questa
By default, if -simulator is not specified, export_simulation will create a
simulator sub-directory for each simulator and export the files for each simulator
in this sub-directory respectively.
IMPORTANT: Please note that the simulation library path must be specified manually
in the generated script for the respective simulator. Please refer to the generated
script header 'Prerequisite' section for more details.
3. Exported script and files
Export simulation will create the driver shell script, setup files and copy the
design sources in the output directory path.
By default, when the -script_name switch is not specified, export_simulation will
create the following script name:-
<simulation_top>.sh (Unix)
When exporting the files for an IP using the -of_objects switch, export_simulation
will create the following script name:-
<ip-name>.sh (Unix)
Export simulation will create the setup files for the target simulator specified
with the -simulator switch.
For example, if the target simulator is "ies", export_simulation will create the
'cds.lib', 'hdl.var' and design library diectories and mappings in the 'cds.lib'
file.
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Vivado 下 IP 核之单端口 RAM 读写
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Vivado 下 IP 核之单端口 RAM 读写 RAM 的英文全称是 Random Access Memory,即随机存取存储器,简称随机存储器,它可以随时把数据 写入任一指定地址的存储单元,也可以随时从任一指定地址的存储单元中读出数据,其读写速度是由时钟频率决定的。本章将向大家介绍 Xilinx RAM IP 核的使用方法并对 RAM IP 核进行简单的读写测试。
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Vivado 下 IP 核之单端口 RAM 读写 (307个子文件)
__synthesis_is_complete__ 0B
__synthesis_is_complete__ 0B
xsim.ini.bak 30KB
elaborate.bat 1KB
simulate.bat 975B
compile.bat 899B
runme.bat 229B
runme.bat 229B
xsim_1.c 11KB
xsim.dbg 77KB
ila_0.dcp 574KB
ila_0.dcp 574KB
ila_0.dcp 573KB
blk_mem_gen_0.dcp 28KB
blk_mem_gen_0.dcp 28KB
blk_mem_gen_0.dcp 28KB
compile.do 750B
compile.do 736B
compile.do 716B
compile.do 712B
compile.do 680B
compile.do 678B
compile.do 670B
compile.do 664B
simulate.do 334B
simulate.do 333B
simulate.do 333B
simulate.do 296B
simulate.do 287B
simulate.do 287B
elaborate.do 213B
simulate.do 196B
simulate.do 180B
elaborate.do 175B
wave.do 32B
wave.do 32B
wave.do 32B
wave.do 32B
wave.do 32B
wave.do 32B
wave.do 32B
wave.do 32B
simulate.do 11B
simulate.do 11B
xsimk.exe 116KB
run.f 505B
run.f 485B
run.f 448B
run.f 432B
usage_statistics_ext_xsim.html 3KB
.xsim_webtallk.info 64B
xsim.ini 30KB
xsim.ini 29KB
xsim.ini 29KB
xsimSettings.ini 1KB
webtalk.jou 985B
webtalk_8984.backup.jou 984B
vivado.jou 828B
vivado.jou 772B
ISEWrap.js 8KB
ISEWrap.js 8KB
rundef.js 1KB
rundef.js 1KB
runme.log 30KB
runme.log 20KB
webtalk.log 1KB
webtalk_8984.backup.log 1KB
elaborate.log 1KB
xvlog.log 1KB
compile.log 1KB
summary.log 899B
summary.log 899B
summary.log 899B
summary.log 899B
summary.log 899B
summary.log 899B
summary.log 899B
summary.log 899B
summary.log 899B
summary.log 899B
simulate.log 728B
xsimkernel.log 336B
xsimcrash.log 0B
ip_1port_ram.lpr 343B
xsim.mem 14KB
xsim_0.win64.obj 61KB
xsim_1.win64.obj 7KB
elab.opt 218B
elab.opt 180B
vivado.pb 48KB
vivado.pb 32KB
xelab.pb 2KB
xvlog.pb 2KB
ila_0_utilization_synth.pb 276B
blk_mem_gen_0_utilization_synth.pb 276B
tb_ip_1port_ram_vlog.prj 444B
vlog.prj 208B
vlog.prj 153B
xsim.reloc 12KB
xil_defaultlib.rlx 1000B
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