VHDL 32位超前进位加法器

4 位超前进位加法器：

library ieee;

use ieee.std_logic_1164.all;

use ieee.std_logic_arith.all;

use ieee.std_logic_unsigned.all;

entity add4 is

port (a:in std_logic_vector(3 downto 0);

b:in std_logic_vector(3 downto 0);

begin

sum(0)<=a(0) xor b(0) xor cin;

sum(1)<=a(1) xor b(1) xor c1;

sum(2)<=a(2) xor b(2) xor c2;

sum(3)<=a(3) xor b(3) xor c3;

c1<=(a(0) and b(0)) or ((a(0) or b(0)) and cin);

c2<=g1 or (p1 and c1);

c3<=g2 or (p2 and c2);

g1<=a(1) and b(1);g2<=a(2) and b(2);

p1<=a(1) or b(1);p2<=a(2) or b(2);

use ieee.std_logic_arith.all;

use ieee.std_logic_unsigned.all;

entity test_add4 is

end;

architecture test_add4 of test_add4 is

component add4

port(a:in std_logic_vector(3 downto 0);

b:in std_logic_vector(3 downto 0);

cin:in std_logic;

sum:out std_logic_vector(3 downto 0);

signal cin:std_logic:='0';

signal sum:std_logic_vector(3 downto 0);

signal co: std_logic;

begin

u0 : add4 port map (a,b,cin,sum,co);

a<= "0000"after 100ns,

"1111" after 300ns;

32 位超前进位加法器：

library ieee;

use ieee.std_logic_1164.all;

use ieee.std_logic_arith.all;

use ieee.std_logic_unsigned.all;

entity add32 is

port (a:in std_logic_vector(31 downto 0);

b:in std_logic_vector(31 downto 0);

component add4

port(a:in std_logic_vector(3 downto 0);

b:in std_logic_vector(3 downto 0);

cin:in std_logic;

sum:out std_logic_vector(3 downto 0);

co:out std_logic);

end component;

signal

g1,g2,g3,g4,g5,g6,g7,g8,g9,g10,g11,g12,g13,g14,g15,g16,g17,g18,g19,g20,g

21,g22,g23,g24,g25,g26,g27:std_logic;

signal

c1,c2,c3,c4,c5,c6,c7,c8,c9,c10,c11,c12,c13,c14,c15,c16,c17,c18,c19,c20,c21,

begin

u1:add4

port map(a(3 downto 0),b(3 downto 0),cin,sum(3 downto 0),co3);

u2:add4

port map(a(7 downto 4),b(7 downto 4),c4,sum(7 downto 4),co7);

u3:add4

port map(a(11 downto 8),b(11 downto 8),c8,sum(11 downto 8),co11);

u4:add4

port map(a(15 downto 12),b(15 downto 12),c12,sum(15 downto 12),co15);

u5:add4