五 MIPS®架构程序员卷IA:介绍MIPS32®架构,修订版6.01
5.3.3:跳转和转移指令.......................................... .................................................. .............. 64
5.3.3.1:第6个紧凑型分支和跳转指令....................................... ........................ 64
5.3.3.2:延迟转移指令........................................... .................................................. ...... 66
5.4:地址计算和大的恒定说明(第6版)...................................... .................. 67
5.5:其他指令.............................................. .................................................. ........................ 68
5.5.1:指令序列化(SYNC和SYNCI)....................................... ............................................. 68
5.5.2:异常说明............................................ .................................................. ........................ 69
5.5.3:条件移动指令........................................... .................................................. ............. 70
5.5.4:预取指令............................................ .................................................. .......................... 70
5.5.5:NOP指令............................................ .................................................. ................................ 71
5.6:协处理器指令.............................................. .................................................. ........................... 71
5.6.1:什么协处理器待办事项........................................... .................................................. ....................... 71
5.6.2:系统控制协处理器0(CP0)....................................... .................................................. ..... 72
5.6.3:浮点协处理器1(CP1)....................................... .................................................. ....... 72
5.6.3.1:协处理器装载和存储指令......................................... ..................................... 72
5.7:CPU指令格式............................................. .................................................. ............................ 73
5.7.1:高级指令编码(第6版)....................................... ........................................... 73
5.7.2:CPU指令字段格式.......................................... .................................................. ............. 74
第6章:FPU编程模型............................................ .................................................. .... 77
6.1:启用浮点协处理器........................................... .................................................. ..... 77
6.2:IEEE标准754 ............................................. .................................................. ..................................... 77
6.3:FPU数据类型............................................. .................................................. ......................................... 78
6.3.1:浮点格式........................................... .................................................. ........................ 78
6.3.1.1:标准化和非标准化的数字.......................................... ...................................... 81
6.3.1.2:保留使用操作数值,无穷大和NaN ....................................... ................................. 81
6.3.1.3:超越无限........................................... .................................................. .................... 81
6.3.1.4:信令非数(SNAN)....................................... .................................................. .... 81
6.3.1.5:静默非数(QNAN)....................................... .................................................. ........... 82
6.3.1.6:配对单例外.......................................... .................................................. ........... 83
6.3.1.7:配对单条件码......................................... .................................................. ... 83
6.3.2:定点格式........................................... .................................................. ............................ 83
6.4:浮点寄存器............................................. .................................................. ............................. 84
6.4.1:FPU注册模型........................................... .................................................. .......................... 84
6.4.2:二进制数据传输(32位和64位).................................. .................................................. .... 86
6.4.3:FPR中并格式化操作数布局......................................... .................................................. 87 ..
6.5:浮点控制寄存器(FcR)的......................................... .................................................. ........ 87
6.5.1:浮点执行注册(FIR,CP1控制寄存器0)................................. ......... 87
6.5.2:用户浮点寄存器模式控制(UFR,CP1控制寄存器1)
(第5版专用)............................................. .................................................. ......................................... 90
6.5.3:用户否定的FP注册模式控制(UNFR,CP1控制寄存器4)
(删除在版本6)............................................ .................................................. .............................. 91
6.5.4:浮点控制和状态寄存器(FCSR,CP1控制寄存器31)................................ 92
6.5.5:浮点条件码寄存器(FCCR,CP1控制寄存器25)(发行版6)........................... .................................................. ..............................................
.... ........... 96
6.5.6:浮点异常寄存器(FEXR,CP1控制寄存器26).................................. .......... 96
6.5.7:浮点使能寄存器(FENR,CP1控制寄存器28).................................. ............... 97
6.6:格式和浮点数据的大小......................................... .................................................. ...... 97
6.6.1:值的格式用于FP寄存器....................................... .................................................. 97
6.6.2:浮点数据的大小......................................... .................................................. .................. 98
6.7:FPU异常.............................................. .................................................. ......................................... 98
6.7.1:精确异常模式........................................... .................................................. ..................... 98
6.7.2:异常情况............................................ .................................................. ......................... 99