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SPP07N60C3 英飞凌芯片 INFINEON 中文版规格书手册.pdf
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SPP07N60C3 英飞凌芯片 INFINEON 中文版规格书手册
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2009-11-27Rev. 3.2
Page 1
SPP07N60C3
SPI07N60C3, SPA07N60C3
Cool MOS™
Power Transistor
V
DS
@ T
jmax
650 V
R
DS(on)
0.6 Ω
I
D
7.3 A
Feature
• New revolutionary high voltage technology
• Ultra low gate charge
• Periodic avalanche rated
• Extreme dv/dt rated
• High peak current capability
• Improved transconductance
•
PG-TO-220-3-31;-3-111: Fully isolated package (2500 VAC; 1 minute)
PG-TO220PG-TO220FP PG-TO262
2
P-TO220-3-1
2
3
1
P-TO220-3-31
1
2
3
Marking
07N60C3
07N60C3
07N60C3
Type Package
Ordering Code
SPP07N60C3
PG-TO220
-3
Q67040-S4400
SPI07N60C3 PG-TO262
Q67040-S4424
SPA07N60C3 PG-TO220FP
SP000216303
Maximum Ratings
Parameter
Symbol
Value
Unit
SPP_I SPA
Continuous drain current
T
C
= 25 °C
T
C
= 100 °C
I
D
7.3
4.6
7.3
1)
4.6
1)
A
Pulsed drain current, t
p
limited by T
jmax
I
D puls
21.9 21.9
A
Avalanche energy, single pulse
I
D
=5.5A, V
DD
=50V
E
AS
230 230
mJ
Avalanche energy, repetitive t
AR
limited by T
jmax
2)
I
D
=7.3A, V
DD
=50V
E
AR
0.5 0.5
Avalanche current, repetitive
t
AR
limited by
T
j
max
I
AR
7.3 7.3
A
Gate source voltage static
V
GS
±20
±20
V
Gate source voltage AC (f >1Hz)
V
GS
±30
±
30
Power dissipation,
T
C
= 25°C
P
tot
83
32
W
Operating and storage temperature
T
j
,
T
st
g
-55...+150 °C
Reverse diode dv/dt dv/dt 15 V/ns
6)
Rev. 3.3
Page 1
2018-02-13
2009-11-27Rev. 3.2
Page 2
SPP07N60C3
SPI07N60C3, SPA07N60C3
Maximum Ratings
Parameter
Symbol Value Unit
Drain Source voltage slope
V
DS
= 480 V, I
D
= 7.3 A,
T
j
= 125 °C
dv/dt 50 V/ns
Thermal Characteristics
Parameter
Symbol Values Unit
min. typ. max.
Thermal resistance, junction - case
R
thJC
- - 1.5 K/W
Thermal resistance, junction - case, FullPAK R
thJC_FP
- - 3.9
Thermal resistance, junction - ambient, leaded
R
thJA
- - 62
Thermal resistance, junction - ambient, FullPAK R
thJA_FP
- - 80
SMD version, device on PCB:
@ min. footprint
@ 6 cm
2
cooling area
3)
R
thJA
-
-
-
35
62
-
Soldering temperature, wavesoldering
1.6 mm (0.063 in.) from case for 10s
T
sold
- - 260 °C
Electrical Characteristics, at T
j
=25°C unless otherwise specified
Parameter
Symbol Conditions Values Unit
min. typ. max.
Drain-source breakdown voltage
V
(BR)DSS
V
GS
=0V, I
D
=0.25mA
600
- - V
Drain-Source avalanche
breakdown voltage
V
(BR)DS
V
GS
=0V, I
D
=7.3A - 700 -
Gate threshold voltage V
GS(th)
I
D
=350µA, V
GS
=V
DS
2.1 3 3.9
Zero gate voltage drain current I
DSS
V
DS
=600V, V
GS
=0V,
T
j
=25°C
T
j
=150°C
-
-
0.5
-
1
100
µA
Gate-source leakage current I
GSS
V
GS
=30V, V
DS
=0V - - 100 nA
Drain-source on-state resistance R
DS(on)
V
GS
=10V, I
D
=4.6A
T
j
=25°C
T
j
=150°C
-
-
0.54
1.46
0.6
-
Ω
Gate input resistance
R
G
f=1MHz, open drain - 0.8 -
Rev. 3.3
Page 2
2018-02-13
2009-11-27Rev. 3.2
Page 3
SPP07N60C3
SPI07N60C3, SPA07N60C3
Electrical Characteristics, at
T
j
= 25 °C, unless otherwise specified
Parameter
Symbol Conditions Values Unit
min. typ. max.
Characteristics
Transconductance g
fs
V
DS
≥2*I
D
*R
DS(on)max
,
I
D
=4.6A
- 6 - S
Input capacitance C
iss
V
GS
=0V, V
DS
=25V,
f=1MHz
- 790 - pF
Output capacitance C
oss
- 260 -
Reverse transfer capacitance C
rss
- 16 -
Effective output capacitance,
4)
energy related
C
o(er)
V
GS
=0V,
V
DS
=0V to 480V
- 30 -
Effective output capacitance,
5)
time related
C
o(tr)
- 55 -
Turn-on delay time t
d(on)
V
DD
=380V, V
GS
=0/13V,
I
D
=7.3A,
R
G
=12Ω,
T
j
=125°C
- 6 - ns
Rise time t
r
- 3.5 -
Turn-off delay time t
d(off)
- 60 100
Fall time t
f
- 7 15
Gate Charge Characteristics
Gate to source charge Q
gs
V
DD
=480V, I
D
=7.3A - 3 - nC
Gate to drain charge Q
gd
- 9.2 -
Gate charge total Q
g
V
DD
=480V, I
D
=7.3A,
V
GS
=0 to 10V
- 21 27
Gate plateau voltage V
(plateau)
V
DD
=480V, I
D
=7.3A - 5.5 - V
1
Limited only by maximum temperature
2
Repetitve avalanche causes additional power losses that can be calculated as P
AV
=
E
AR
*
f.
3
Device on 40mm*40mm*1.5mm epoxy PCB FR4 with 6cm² (one layer, 70 µm thick) copper area for drain
connection. PCB is vertical without blown air.
4
C
o(er)
is a fixed capacitance that gives the same stored energy as
C
oss
while
V
DS
is rising from 0 to 80% V
DSS
.
5
C
o(tr)
is a fixed capacitance that gives the same charging time as
C
oss
while
V
DS
is rising from 0 to 80% V
DSS
.
6
I
SD
<=I
D
, di/dt<=400A/us, V
DClink
=400V, V
peak
<V
BR, DSS
, T
j
<T
j,max
.
Identical low-side and high-side switch.
Rev. 3.3
Page 3
2018-02-13
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