【免费】TI-DS15MB200.pdf资源-CSDN文库

5星 · 超过95%的资源需积分: 0 136 浏览量 2023-02-08 23:36:05 上传评论 4 收藏 1.01MB PDF 举报

资源推荐

资源详情

资源评论

Mux Buffer

Switch

Fabric A

Switch

Fabric B

FPGA

ASIC

Backplane or Cable

LVDS

DS15MB200

www.ti.com

SNLS196E –NOVEMBER 2005–REVISED MARCH 2013

DS15MB200 Dual 1.5 Gbps 2:1/1:2 LVDS Mux/Buffer with Pre-Emphasis

Check for Samples: DS15MB200

FEATURES

DESCRIPTION

The DS15MB200 is a dual-port 2 to 1 multiplexer and

• 1.5 Gbps Data Rate Per Channel

1 to 2 repeater/buffer. High-speed data paths and

• Configurable Off/On Pre-emphasis Drives

flow-through pinout minimize internal device jitter and

Lossy Backplanes and Cables

simplify board layout, while pre-emphasis overcomes

• LVDS/BLVDS/CML/LVPECL Compatible Inputs,

ISI jitter effects from lossy backplanes and cables.

The differential inputs and outputs interface to LVDS

LVDS Compatible Outputs

or Bus LVDS signals such as those on Texas

• Low Output Skew and Jitter

Instrument's 10-, 16-, and 18-bit Bus LVDS SerDes,

• On-chip 100Ω Input and Output Termination

or to CML or LVPECL signals.

• 15 kV ESD Protection on LVDS Inputs/Outputs

The 3.3V supply, CMOS process, and robust I/O

• Hot Plug Protection

ensure high performance at low power over the entire

industrial -40 to +85°C temperature range.

• Single 3.3V Supply

• Industrial -40 to +85°C Temperature Range

• 48-pin WQFN Package

Typical Application

Figure 1.

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of

Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

2All trademarks are the property of their respective owners.

PRODUCTION DATA information is current as of publication date.

Products conform to specifications per the terms of the Texas

Instruments standard warranty. Production processing does not

necessarily include testing of all parameters.

Channel 1

Channel 0

LI_0

SOA_0

SOB_0

SIA_0

SIB_0

MUX_S0

PREA_0

ENA_0

PREB_0

ENB_0

LO_0

PREL_0

ENL_0

DS15MB200

SNLS196E –NOVEMBER 2005–REVISED MARCH 2013

www.ti.com

Block Diagram

Figure 2.

PIN DESCRIPTIONS

Pin WQFN Pin

I/O, Type Description

Name Number

SWITCH SIDE DIFFERENTIAL INPUTS

SIA_0+ 30 I, LVDS Switch A-side Channel 0 inverting and non-inverting differential inputs. LVDS, Bus LVDS, CML, or

SIA_0− 29 LVPECL compatible.

SIA_1+ 19 I, LVDS Switch A-side Channel 1 inverting and non-inverting differential inputs. LVDS, Bus LVDS, CML, or

SIA_1− 20 LVPECL compatible.

SIB_0+ 28 I, LVDS Switch B-side Channel 0 inverting and non-inverting differential inputs. LVDS, Bus LVDS, CML, or

SIB_0− 27 LVPECL compatible.

SIB_1+ 21 I, LVDS Switch B-side Channel 1 inverting and non-inverting differential inputs. LVDS, Bus LVDS, CML, or

SIB_1− 22 LVPECL compatible.

LINE SIDE DIFFERENTIAL INPUTS

LI_0+ 40 I, LVDS Line-side Channel 0 inverting and non-inverting differential inputs. LVDS, Bus LVDS, CML, or

LI_0− 39 LVPECL compatible.

LI_1+ 9 I, LVDS Line-side Channel 1 inverting and non-inverting differential inputs. LVDS, Bus LVDS, CML, or

LI_1− 10 LVPECL compatible.

SWITCH SIDE DIFFERENTIAL OUTPUTS

SOA_0+ 34 O, LVDS Switch A-side Channel 0 inverting and non-inverting differential outputs. LVDS compatible

(1)(2)

SOA_0− 33

SOA_1+ 15 O, LVDS Switch A-side Channel 1 inverting and non-inverting differential outputs. LVDS compatible

(1)(2)

SOA_1− 16

SOB_0+ 32 O, LVDS Switch B-side Channel 0 inverting and non-inverting differential outputs. LVDS compatible

(1)(2)

SOB_0− 31

SOB_1+ 17 O, LVDS Switch B-side Channel 1 inverting and non-inverting differential outputs. LVDS compatible

(1)(2)

SOB_1− 18

LINE SIDE DIFFERENTIAL OUTPUTS

LO_0+ 42 O, LVDS Line-side Channel 0 inverting and non-inverting differential outputs. LVDS compatible

(1)(2)

LO_0− 41

LO_1+ 7 O, LVDS Line-side Channel 1 inverting and non-inverting differential outputs. LVDS compatible

(1)(2)

LO_1− 8

(1) For interfacing LVDS outputs to CML or LVPECL compatible inputs, refer to the applications section of this datasheet (planned).

(2) The LVDS outputs do not support a multidrop (BLVDS) environment. The LVDS output characteristics of the DS15MB200 device have

been optimized for point-to-point backplane and cable applications.

Product Folder Links: DS15MB200

GND

ENL_0

PREL_0

LO_0+

LO_0-

LI_0+

LI_0-

MUX_S0

ENA_1

ENB_1

SOA_1+

SOA_1-

SOB_1+

SOB_1-

SIA_1+

SIA_1-

SIB_1+

SIB_1-

PREA_1

PREB_1

MUX_S1

LI_1-

LI_1+

LO_1-

LO-1+

PREL_1

ENL_1

GND

N/C

12 11 10 9 8 7 6 5 4 3 2 1

PREB_0

PREA_0

SIB_0-

SIB_0+

SIA_0-

SIA_0+

SOB_0-

SOB_0+

SOA_0-

SOA_0+

ENB_0

ENA_0

25 26 27 28 29 30 31 32 33 34 35 36

DAP

(GND)

GND

ENL_0

PREL_0

LO_0+

LO_0-

LI_0+

LI_0-

MUX_S0

ENA_1

ENB_1

SOA_1+

SOA_1-

SOB_1+

SOB_1-

SIA_1+

SIA_1-

SIB_1+

SIB_1-

PREA_1

PREB_1

MUX_S1

LI_1-

LI_1+

LO_1-

LO-1+

PREL_1

ENL_1

GND

N/C

PREB_0

PREA_0

SIB_0-

SIB_0+

SIA_0-

SIA_0+

SOB_0-

SOB_0+

SOA_0-

SOA_0+

ENB_0

ENA_0

Channel 0

Channel 1

DS15MB200

www.ti.com

SNLS196E –NOVEMBER 2005–REVISED MARCH 2013

PIN DESCRIPTIONS (continued)

Pin WQFN Pin

I/O, Type Description

Name Number

DIGITAL CONTROL INTERFACE

MUX_S0 38 I, LVTTL Mux Select Control Inputs (per channel) to select which Switch-side input, A or B, is passed through

MUX_S1 11 to the Line-side.

PREA_0 26 I, LVTTL Output pre-emphasis control for Switch-side outputs. Each output driver on the Switch A-side and B-

PREA_1 23 side has a separate pin to control the pre-emphasis on or off.

PREB_0 25

PREB_1 24

PREL_0 44 I, LVTTL Output pre-emphasis control for Line-side outputs. Each output driver on the Line A-side and B-side

PREL_1 5 has a separate pin to control the pre-emphasis on or off.

ENA_0 36 I, LVTTL Output Enable Control for Switch A-side and B-side outputs. Each output driver on the A-side and

ENA_1 13 B-side has a separate enable pin.

ENB_0 35

ENB_1 14

ENL_0 45 I, LVTTL Output Enable Control for The Line-side outputs. Each output driver on the Line-side has a separate

ENL_1 4 enable pin.

POWER

2, 6, 12, I, Power V

= 3.3V ±0.3V.

37, 43, 46,

GND 3, 47

(3)

I, Power Ground reference for LVDS and CMOS circuitry.

For the WQFN package, the DAP is used as the primary GND connection to the device. The DAP is

the exposed metal contact at the bottom of the WQFN-48 package. It should be connected to the

ground plane with at least 4 vias for optimal AC and thermal performance.

(3) Note that the DAP on the backside of the WQFN package is the primary GND connection for the device when using the WQFN

package.

Connection Diagrams

Figure 3. WQFN Top View Figure 4. Directional Signal Paths Top View

DAP = GND (Refer to pin names for signal polarity)

Product Folder Links: DS15MB200

剩余19页未读，继续阅读

评论收藏

内容反馈

qq_33560727

2023-02-15

#完美解决问题 #运行顺畅 #内容详尽 #全网独家 #注释完整
m0_74525996

2023-02-15

#完美解决问题 #运行顺畅 #内容详尽 #全网独家 #注释完整

不觉明了

粉丝: 3242
资源: 5614

TI-DS15MB200.pdf

TI-REF200.pdf

TI-CD74HC4543.pdf

TI-SN75LVPE801.pdf

TI-TL16C550C.pdf

TI-TPS658640.pdf

TI-DS15EA101.pdf

TI-DS15BA101.pdf

TI-DS15BR401.pdf

新ds15.zip

TI-TPS51116.pdf

TI-PGA2505.pdf

TI-TPS55289.pdf

TI-AFE5812.pdf

TI-TPS1663.pdf

NS推出LVDS多路转换器/缓冲器二合一芯片

HP AlphaServer DS15系统配置手册

国半延长电缆芯片组DS15BA101和DS15EA101功耗仅360mW

通信与网络中的NS推出4通道LVDS缓冲器/中继器DS15BR400/1

NCP5662DS15R4G的技术参数

TI-LMH34400.pdf

TI-UCD3040.pdf

TI-LMH1981.pdf

TI-TPS23861.pdf

TI-TMUX1309.pdf

Alpha install

论文研究 - 过量碳化物的分布对纯正大马士革钢性能的影响

NS推出最低功率而又容易使用的延长电缆芯片组

NS推出最低功率而又易使用的延长电缆芯片组

通信与网络中的NSC的4通道LVDS缓冲器/中继器具有极低的信号抖动

最新资源