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Mux Buffer

Switch

Fabric A

Switch

Fabric B

FPGA

ASIC

Backplane or Cable

LVDS

SCAN15MB200

www.ti.com

SNLS188E –NOVEMBER 2005–REVISED APRIL 2013

Dual 1.5 Gbps 2:1/1:2 LVDS Mux/Buffer with Pre-Emphasis and IEEE 1149.6

Check for Samples: SCAN15MB200

FEATURES

DESCRIPTION

The SCAN15MB200 is a dual-port 2 to 1 multiplexer

• 1.5 Gbps Data Rate Per Channel

and 1 to 2 repeater/buffer. High-speed data paths

• Configurable Off/On Pre-emphasis Drives

and flow-through pinout minimize internal device jitter

Lossy Backplanes and Cables

and simplify board layout, while pre-emphasis

• LVDS/BLVDS/CML/LVPECL Compatible Inputs,

overcomes ISI jitter effects from lossy backplanes

and cables. The differential inputs and outputs

LVDS Compatible Outputs

interface to LVDS or Bus LVDS signals such as those

• Low Output Skew and Jitter

on TI's 10-, 16-, and 18- bit Bus LVDS SerDes, or to

• On-chip 100Ω Input and Output Termination

CML or LVPECL signals.

• IEEE 1149.1 and 1149.6 Compliant

Integrated IEEE 1149.1 (JTAG) and 1149.6 circuitry

• 15 kV ESD Protection on LVDS Inputs/Outputs

supports testability of both single-ended

LVTTL/CMOS and high-speed differential PCB

• Hot Plug Protection

interconnects. The 3.3V supply, CMOS process, and

• Single 3.3V Supply

robust I/O ensure high performance at low power

• Industrial -40 to +85°C Temperature Range

over the entire industrial -40 to +85°C temperature

• 48-Pin WQFN Package

range.

Typical Application

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of

Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

2All trademarks are the property of their respective owners.

PRODUCTION DATA information is current as of publication date.

Products conform to specifications per the terms of the Texas

Instruments standard warranty. Production processing does not

necessarily include testing of all parameters.

Channel 1

LI_0

SOA_0

SOB_0

SIA_0

SIB_0

MUX_S0

PREA_0

ENA_0

PREB_0

ENB_0

Channel 0

LO_0

PREL_0

IEEE 1149.1 (JTAG)

Test Access Port,

1149.6, Fault Insertion

TDI

TDO

TCK

TMS

TRST

ENL_0

SCAN15MB200

SNLS188E –NOVEMBER 2005–REVISED APRIL 2013

www.ti.com

Block Diagram

Figure 1. SCAN15MB200 Block Diagram

Pin Descriptions

Pin WQFN Pin

I/O, Type Description

Name Number

SWITCH SIDE DIFFERENTIAL INPUTS

SIA_0+ 30 I, LVDS Switch A-side Channel 0 inverting and non-inverting differential inputs. LVDS, Bus LVDS, CML, or

SIA_0− 29 LVPECL compatible.

SIA_1+ 19 I, LVDS Switch A-side Channel 1 inverting and non-inverting differential inputs. LVDS, Bus LVDS, CML, or

SIA_1− 20 LVPECL compatible.

SIB_0+ 28 I, LVDS Switch B-side Channel 0 inverting and non-inverting differential inputs. LVDS, Bus LVDS, CML, or

SIB_0− 27 LVPECL compatible.

SIB_1+ 21 I, LVDS Switch B-side Channel 1 inverting and non-inverting differential inputs. LVDS, Bus LVDS, CML, or

SIB_1− 22 LVPECL compatible.

LINE SIDE DIFFERENTIAL INPUTS

LI_0+ 40 I, LVDS Line-side Channel 0 inverting and non-inverting differential inputs. LVDS, Bus LVDS, CML, or

LI_0− 39 LVPECL compatible.

LI_1+ 9 I, LVDS Line-side Channel 1 inverting and non-inverting differential inputs. LVDS, Bus LVDS, CML, or

LI_1− 10 LVPECL compatible.

SWITCH SIDE DIFFERENTIAL OUTPUTS

SOA_0+ 34 O, LVDS Switch A-side Channel 0 inverting and non-inverting differential outputs. LVDS compatible

(1) (2)

SOA_0− 33

SOA_1+ 15 O, LVDS Switch A-side Channel 1 inverting and non-inverting differential outputs. LVDS compatible

(1) (2)

SOA_1− 16

SOB_0+ 32 O, LVDS Switch B-side Channel 0 inverting and non-inverting differential outputs. LVDS compatible

(1) (2)

SOB_0− 31

SOB_1+ 17 O, LVDS Switch B-side Channel 1 inverting and non-inverting differential outputs. LVDS compatible

(1) (2)

SOB_1− 18

(1) For interfacing LVDS outputs to CML or LVPECL compatible inputs, refer to the applications section of this datasheet (planned).

(2) The LVDS outputs do not support a multidrop (BLVDS) environment. The LVDS output characteristics of the SCAN15MB200 device

have been optimized for point-to-point backplane and cable applications.

Product Folder Links: SCAN15MB200

SCAN15MB200

www.ti.com

SNLS188E –NOVEMBER 2005–REVISED APRIL 2013

Pin Descriptions (continued)

Pin WQFN Pin

I/O, Type Description

Name Number

LINE SIDE DIFFERENTIAL OUTPUTS

LO_0+ 42 O, LVDS Line-side Channel 0 inverting and non-inverting differential outputs. LVDS compatible

(3) (4)

LO_0− 41

LO_1+ 7 O, LVDS Line-side Channel 1 inverting and non-inverting differential outputs. LVDS compatible

(3) (4)

LO_1− 8

DIGITAL CONTROL INTERFACE

MUX_S0 38 I, LVTTL Mux Select Control Inputs (per channel) to select which Switch-side input, A or B, is passed through

MUX_S1 11 to the Line-side.

PREA_0 26 I, LVTTL Output pre-emphasis control for Switch-side outputs. Each output driver on the Switch A-side and B-

PREA_1 23 side has a separate pin to control the pre-emphasis on or off.

PREB_0 25

PREB_1 24

PREL_0 44 I, LVTTL Output pre-emphasis control for Line-side outputs. Each output driver on the Line A-side and B-side

PREL_1 5 has a separate pin to control the pre-emphasis on or off.

ENA_0 36 I, LVTTL Output Enable Control for Switch A-side and B-side outputs. Each output driver on the A-side and

ENA_1 13 B-side has a separate enable pin.

ENB_0 35

ENB_1 14

ENL_0 45 I, LVTTL Output Enable Control for The Line-side outputs. Each output driver on the Line-side has a separate

ENL_1 4 enable pin.

TDI 2 I, LVTTL Test Data Input to support IEEE 1149.1 features

TDO 1 O, LVTTL Test Data Output to support IEEE 1149.1 features

TMS 46 I, LVTTL Test Mode Select to support IEEE 1149.1 features

TCK 47 I, LVTTL Test Clock to support IEEE 1149.1 features

TRST 3 I, LVTTL Test Reset to support IEEE 1149.1 features

POWER

6, 12, 37, I, Power V

= 3.3V ±0.3V.

43, 48

GND See

(5)

I, Power Ground reference for LVDS and CMOS circuitry.

For the WQFN package, the DAP is used as the primary GND connection to the device. The DAP is

the exposed metal contact at the bottom of the WQFN-48 package. It should be connected to the

ground plane with at least 4 vias for optimal AC and thermal performance.

(3) For interfacing LVDS outputs to CML or LVPECL compatible inputs, refer to the applications section of this datasheet (planned).

(4) The LVDS outputs do not support a multidrop (BLVDS) environment. The LVDS output characteristics of the SCAN15MB200 device

have been optimized for point-to-point backplane and cable applications.

(5) Note that the DAP on the backside of the WQFN package is the primary GND connection for the device when using the WQFN

package.

Product Folder Links: SCAN15MB200

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