【免费】TI-DS25MB200.pdf资源-CSDN文库

5星 · 超过95%的资源需积分: 0 165 浏览量 2023-02-08 23:34:12 上传评论 4 收藏 844KB PDF 举报

资源推荐

资源详情

资源评论

PRE_S

LO_0 ±

MUX_S0

SIA_0 ±

SIB_0 ±

LB0A

LB0B

SOA_0 ±

SOB_0 ±

LI_0 ±

PRE_S

PRE_L

PRE_S

LO_1 ±

MUX_S1

SIA_1 ±

SIB_1 ±

LB1A

LB1B

SOA_1 ±

SOB_1 ±

LI_1 ±

PRE_S

PRE_L

Pre-emphasis

Control

PreL_0

PreS_1

PreS_0

PreL_1

PRE_S

PRE_L

GND

Port 0

Port 1

RSV

Switch Side

Line Side

DS25MB200

www.ti.com

SNLS220G –MARCH 2006–REVISED APRIL 2013

DS25MB200 Dual 2.5 Gbps 2:1/1:2 CML Mux/Buffer with Transmit Pre-Emphasis and

Receive Equalization

Check for Samples: DS25MB200

FEATURES

DESCRIPTION

The DS25MB200 is a dual signal conditioning 2:1

• 0.6–2.5 Gbps Low Jitter Operation

multiplexer and 1:2 fan-out buffer designed for use in

• Fixed Input Equalization

backplane redundancy applications. Signal

• Programmable Output Pre-Emphasis

conditioning features include input equalization and

programmable output pre-emphasis that enable data

• Independent Switch and Line Side Pre-

communication in FR4 backplanes up to 2.5 Gbps.

Emphasis Controls

Each input stage has a fixed equalizer to reduce ISI

• Programmable Switch-Side Loopback Modes

distortion from board traces. All output drivers have 4

• On-Chip Terminations

selectable steps of pre-emphasis to compensate for

transmission losses from long FR4 backplanes and

• HBM ESD Rating 6 kV on All Pins

reduce deterministic jitter. The pre-emphasis levels

• +3.3V Supply

can be independently controlled for the line-side and

• Lead-Less WQFN-48 Package (7mm x 7mm x

switch-side drivers. The internal loopback paths from

0.8mm, 0.5mm Pitch)

switch-side input to switch-side output enable at-

speed system testing. All receiver inputs are internally

• -40°C to +85°C Operating Temperature Range

terminated with 100Ω differential terminating

resistors. All drivers are internally terminated with

APPLICATIONS

50Ω to V

• Backplane or Cable Driver

• Redundancy and Signal Conditioning

Applications

Functional Block Diagram

All CML inputs and outputs must be AC coupled for optimal performance.

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of

Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

2All trademarks are the property of their respective owners.

PRODUCTION DATA information is current as of publication date.

Products conform to specifications per the terms of the Texas

Instruments standard warranty. Production processing does not

necessarily include testing of all parameters.

13 14 15 16 17 18 2019 21 22

48 47 46 45 44 43 4142 40 39

SOB_0-

SOB_0+

GND

LI_0+

LI_0-

LO_1+

LO_1-

GND

PreL1

WQFN-48

Top View Shown

DAP = GND

12PreL0

SIA_1+

LB1A

SOA_1+

SOA_1-

SIB_1+

SIB_1-

GND

SIA_1-

MUX_S1

LB1B

SOA_0-

LB0A

SIA_0-

SIA_0+

GND

SIB_0-

SIB_0+

LB0B

SOA_0+

MUX_S0

LO_0-

LO_0+

GND

LI_1-

LI_1+

SOB_1+

RSV

SOB_1-

PreS0

PreS1

DS25MB200

www.ti.com

SNLS220G –MARCH 2006–REVISED APRIL 2013

Connection Diagram

Figure 1. 48 Pin (Top View)

See Package Number NJU0048D

PIN DESCRIPTIONS

(1)

Pin Name Pin Number I/O

(2)

Description

LINE SIDE HIGH SPEED DIFFERENTIAL IO's

LI_0+ 6 I Inverting and non-inverting differential inputs of port_0 at the line side. LI_0+ and LI_0− have an

LI_0− 7 internal 50Ω connected to an internal reference voltage. See Figure 7.

LO_0+ 33 O Inverting and non-inverting differential outputs of port_0 at the line side. LO_0+ and LO_0− have an

LO_0− 34 internal 50Ω connected to V

LI_1+ 30 I Inverting and non-inverting differential inputs of port_1 at the line side. LI_1+ and LI_1− have an

LI_1− 31 internal 50Ω connected to an internal reference voltage. See Figure 7.

LO_1+ 9 O Inverting and non-inverting differential outputs of port_1 at the line side. LO_1+ and LO_1− have an

LO_1− 10 internal 50Ω connected to V

SWITCH SIDE HIGH SPEED DIFFERENTIAL IO's

SOA_0+ 46 O Inverting and non-inverting differential outputs of mux_0 at the switch_A side. SOA_0+ and SOA_0−

SOA_0− 45 have an internal 50Ω connected to V

SOB_0+ 4 O Inverting and non-inverting differential outputs of mux_0 at the switch_B side. SOB_0+ and SOB_0−

SOB_0− 3 have an internal 50Ω connected to V

SIA_0+ 40 I Inverting and non-inverting differential inputs to the mux_0 at the switch_A side. SIA_0+ and SIA_0−

SIA_0− 39 have an internal 50Ω connected to an internal reference voltage. See Figure 7.

SIB_0+ 43 I Inverting and non-inverting differential inputs to the mux_0 at the switch_B side. SIB_0+ and SIB_0−

SIB_0− 42 have an internal 50Ω connected to an internal reference voltage. See Figure 7.

(1) All CML Inputs or Outputs must be AC coupled.

(2) I = Input, O = Output, P = Power

Product Folder Links: DS25MB200

DS25MB200

SNLS220G –MARCH 2006–REVISED APRIL 2013

www.ti.com

PIN DESCRIPTIONS

(1)

(continued)

Pin Name Pin Number I/O

(2)

Description

SOA_1+ 22 O Inverting and non-inverting differential outputs of mux_1 at the switch_A side. SOA_1+ and SOA_1−

SOA_1− 21 have an internal 50Ω connected to V

SOB_1+ 28 O Inverting and non-inverting differential outputs of mux_1 at the switch_B side. SOB_1+ and SOB_1−

SOB_1− 27 have an internal 50Ω connected to V

SIA_1+ 16 I Inverting and non-inverting differential inputs to the mux_1 at the switch_A side. SIA_1+ and SIA_1−

SIA_1− 15 have an internal 50Ω connected to an internal reference voltage. See Figure 7.

SIB_1+ 19 I Inverting and non-inverting differential inputs to the mux_1 at the switch_B side. SIB_1+ and SIB_1−

SIB_1− 18 have an internal 50Ω connected to an internal reference voltage. See Figure 7.

CONTROL (3.3V LVCMOS)

MUX_S0 37 I A logic low at MUX_S0 selects mux_0 to switch B. MUX_S0 is internally pulled high. Default state for

mux_0 is switch A.

MUX_S1 13 I A logic low at MUX_S1 selects mux_1 to switch B. MUX_S0 is internally pulled high. Default state for

mux_1 is switch A.

PREL_0 12 I PREL_0 and PREL_1 select the output pre-emphasis of the line side drivers (LO_0± and LO_1±).

PREL_1 1 PREL_0 and PREL_1 are internally pulled high. See Table 3 for line side pre-emphasis levels.

PRES_0 36 I PRES_0 and PRES_1 select the output pre-emphasis of the switch side drivers (SOA_0±, SOB_0±,

PRES_1 25 SOA_1± and SOB_1±). PRES_0 and PRES_1 are internally pulled high. See Table 4 for switch side

pre-emphasis levels.

LB0A 47 I A logic low at LB0A enables the internal loopback path from SIA_0± to SOA_0±. LB0A is internally

pulled high.

LB0B 48 I A logic low at LB0B enables the internal loopback path from SIB_0± to SOB_0±. LB0B is internally

pulled high.

LB1A 23 I A logic low at LB1A enables the internal loopback path from SIA_1± to SOA_1±. LB1A is internally

pulled high.

LB1B 24 I A logic low at LB1B enables the internal loopback path from SIB_1± to SOB_1±. LB1B is internally

pulled high.

RSV 26 I Reserve pin to support factory testing. This pin can be left open, or tied to GND, or tied to GND

through an external pull-down resistor.

POWER

2, 8, 14, 20, P V

= 3.3V ± 5%.

29, 35, 38, Each V

pin should be connected to the V

plane through a low inductance path, typically with a

44 via located as close as possible to the landing pad of the V

pin.

It is recommended to have a 0.01 μF or 0.1 μF, X7R, size-0402 bypass capacitor from each V

to ground plane.

GND 5, 11, 17, 32, P Ground reference. Each ground pin should be connected to the ground plane through a low

41 inductance path, typically with a via located as close as possible to the landing pad of the GND pin.

GND DAP P Die Attach Pad (DAP) is the metal contact at the bottom side, located at the center of the WQFN-48

package. It should be connected to the GND plane with at least 4 via to lower the ground impedance

and improve the thermal performance of the package.

Functional Description

The DS25MB200 is a signal conditioning 2:1 multiplexer and a 1:2 buffer designed to support port redundancy up

to 2.5 Gbps. The high speed inputs are self-biased to about 1.3V and are designed for AC coupling. See

Figure 7 for details. The inputs are compatible to most AC coupling differential signals such as LVDS, LVPECL

and CML. The DS25MB200 is not designed to operate with data rates below 250 Mbps or with a DC bias applied

to the CML inputs or outputs. Most high speed links are encoded for DC balance and have been defined to

include AC coupling capacitors allowing the DS25MB200 to be directly inserted into the datapath without any

limitation. The ideal AC coupling capacitor value is often based on the lowest frequency component embedded

within the serial link. A typical AC coupling capacitor value ranges between 100 and 1000nF. Some

specifications with scrambled data may require a larger capacitor for optimal performance. To reduce unwanted

parasitics around and within the AC coupling capacitor, a body size of 0402 is recommended. Figure 6 shows the

AC coupling capacitor placement in an AC test circuit.

Product Folder Links: DS25MB200

剩余15页未读，继续阅读

评论收藏

内容反馈

qq_33560727

2023-02-15

#完美解决问题 #运行顺畅 #内容详尽 #全网独家 #注释完整
m0_74525996

2023-02-15

#完美解决问题 #运行顺畅 #内容详尽 #注释完整
CSDN_187

2023-02-15

#完美解决问题 #运行顺畅 #内容详尽 #全网独家 #注释完整
2301_76396056

2023-02-15

#完美解决问题 #运行顺畅 #内容详尽 #全网独家 #注释完整

不觉明了

粉丝: 3230
资源: 5614

TI-DS25MB200.pdf

TI-ADC32RF54.pdf

TI-CD74HC4543.pdf

TI-SN75LVPE801.pdf

TI-TL16C550C.pdf

TI-AFE58JD16.pdf

TI-DS25CP102.pdf

TI-DS25CP114.pdf

TI-DS25CP102Q-Q1.pdf

TI-DS25CP152Q-Q1.pdf

TI-UCC24636.pdf

TI-TPS658640.pdf

TI-UCC28710.pdf

TI-TPS51116.pdf

TI-UCC28911.pdf

TI-DS25MB100.pdf

TI-DS25BR101.pdf

TI-DS25BR204.pdf

TI-DS25BR440.pdf

TI-DS25BR120.pdf

TI-SN7489J.pdf

TI-TPS65983B.pdf

TI-TPS55289.pdf

TI-TPS92390.pdf

TI-VCA8500.pdf

TI-DS25BR150.pdf

HP AlphaServer DS25系统配置手册

HP AlphaServer DS25系统技术概览

NS推出三款全新信号调节缓冲器DS25BR100\10\20

通信与网络中的NS推出首款设有均衡及预加重功能而且信号完整性的LVDS缓冲器

最新资源