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TI-SN65LVCP40.pdf
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TI-SN65LVCP40.pdf
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www.ti.com
FEATURES
APPLICATIONS
DESCRIPTION
FUNCTIONAL DIAGRAM
Programmable
Preemphasis
Output Data
EQ
out
Input Equalization
Opens up Data Eye
Input Data After Long Backplane Trace
SN65LVCP40
SLLS623D – SEPTEMBER 2004 – REVISED FEBRUARY 2006
DC TO 4-GBPS DUAL 1:2 MULTIPLEXER/REPEATER/EQUALIZER
• 48-Terminal QFN (Quad Flatpack)
7 mm × 7 mm × 1 mm, 0.5-mm Terminal Pitch
• Receiver Equalization and Selectable Driver
Preemphasis to Counteract High-Frequency • Temperature Range: -40 ° C to 85 ° C
Transmission Line Losses
• Integration of Two-Serial Port
• Bidirectional Link Replicator
• Selectable Loopback
• Signal Conditioner
• Typical Power Consumption 650 mW
• XAUI 802.3ae Protocol Backplane
• 30-ps Deterministic Jitter
Redundancy
• On-Chip 100- Ω Receiver and Driver
• Host Adapter (Applications With Internal and
Differential Termination Resistors Eliminate
External Connection to SERDES)
External Components and Reflection from
• Signaling Rates DC to 4 Gbps Including XAUI,
Stubs
GbE, FC, HDTV
• 3.3-V Nominal Power Supply
The SN65LVCP40 is a signal conditioner and data multiplexer optimized for backplanes. Input equalization and
programmable output preemphasis support data rates up to 4 Gbps. Common applications are redundancy
switching, signal buffering, or performance improvements on legacy backplane hardware.
The SN65LVCP40 combines a pair of 1:2 buffers with a pair of 2:1 multiplexers (mux). Selectable switch-side
loopback supports system testing. System interconnects and serial backplane applications of up to 4 Gbps are
supported. Each of the two independent channels consists of a transmitter with a fan-out of two, and a receiver
with a 2:1 input multiplexer.
The drivers provide four selectable levels of preemphasis to compensate for transmission line losses. The
receivers incorporates receive equalization and compensates for input transmission line loss. This minimizes
deterministic jitter in the link. The equalization is optimized to compensate for a FR-4 backplane trace with 5-dB,
high-frequency loss between 375 MHz and 1.875 GHz. This corresponds to a 24-inch long FR-4 trace with 6-mil
trace width.
This device operates from a single 3.3-V supply. The device has integrated 100- Ω line termination and provides
self-biasing. The input tolerates most differential signaling levels such as LVDS, LVPECL or CML. The output
impedance matches 100- Ω line impedance. The inputs and outputs may be ac coupled for best interconnectivity
with other devices such as SERDES I/O or additional XAUI multiplexer buffer. With ac coupling, jitter is the
lowest.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date.
Copyright © 2004–2006, Texas Instruments Incorporated
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
www.ti.com
DESCRIPTION (CONTINUED)
ABSOLUTE MAXIMUM RATINGS
PACKAGE THERMAL CHARACTERISTICS
SN65LVCP40
SLLS623D – SEPTEMBER 2004 – REVISED FEBRUARY 2006
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
The SN65LVCP40 is packaged in a 7 mm × 7 mm × 1 mm QFN (quad flatpack no-lead) lead-free package, and
is characterized for operation from -40°C to 85°C.
AVAILABLE OPTIONS
PACKAGED DEVICE
(1)
T
A
DESCRIPTION
RGZ (48 pin)
-40 °C to 85 °C Serial multiplexer SN65LVCP40
(1) The package is available taped and reeled. Add an R suffix to device types (e.g., SN65LVCP40RGZR).
over operating free-air temperature range (unless otherwise noted)
(1)
UNIT
V
CC
Supply voltage range
(2)
–0.5 V to 6 V
Control inputs, all outputs –0.5 V to (V
CC
+ 0.5 V)
Voltage range
Receiver inputs –0.5 V to 4 V
Human Body Model
(3)
All pins 4 kV
ESD
Charged-Device Model
(4)
All pins 500 V
See Package Thermal Characteristics
T
J
Maximum junction temperature
Table
(1) Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings
only and functional operation of the device at these or any other conditions beyond those indicated under recommended operating
conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) All voltage values, except differential I/O bus voltages, are with respect to network ground terminal.
(3) Tested in accordance with JEDEC Standard 22, Test Method A114-A.
(4) Tested in accordance with JEDEC Standard 22, Test Method C101.
PACKAGE THERMAL CHARACTERISTICS
(1)
NOM UNIT
θ
JA
(junction-to-ambient) 33 °C/W
θ
JB
(junction-to-board) 20 °C/W
4-layer JEDEC Board (JESD51-7) using eight GND-vias Ø-0.2 on the
θ
JC
(junction-to-case) 23.6 °C/W
center pad as shown in the section: Recommended pcb footprint with
PSI-jt (junction-to-top pseudo) 0.6 °C/W
boundary and environment conditions of JEDEC Board (JESD51-2)
PSI-jb (junction-to-board pseudo) 19.4 °C/W
θ
JP
(junction-to-pad) 5.4 °C/W
(1) See application note SPRA953 for a detailed explanation of thermal parameters (http://www-s.ti.com/sc/psheets/spra953/spra953.pdf ).
2
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RECOMMENDED OPERATING CONDITIONS
V
CC
|V
ID
|
2
ELECTRICAL CHARACTERISTICS
SN65LVCP40
SLLS623D – SEPTEMBER 2004 – REVISED FEBRUARY 2006
MIN NOM MAX UNIT
dR Operating data rate 4 Gbps
V
CC
Supply voltage 3.135 3.3 3.465 V
V
CC(N)
Supply voltage noise amplitude 10 Hz to 2 GHz 20 mV
T
J
Junction temperature 125 °C
T
A
Operating free-air temperature
(1)
-40 85 °C
DIFFERENTIAL INPUTS
dR
(in)
≤ 1.25 Gbps 100 1750 mVpp
Receiver peak-to-peak differential input
V
ID
1.25 Gbps < dR
(in)
≤ 3.125 Gbps 100 1560 mVpp
voltage
(2)
dR
(in)
> 3.125 Gbps 100 1000 mVpp
Receiver common-mode Note: for best jitter performance ac
V
ICM
1.5 1.6 V
input voltage coupling is recommended.
CONTROL INPUTS
V
IH
High-level input voltage 2 V
CC
+ 0.3 V
V
IL
Low-level input voltage –0.3 0.8 V
DIFFERENTIAL OUTPUTS
R
L
Differential load resistance 80 100 120 Ω
(1) Maximum free-air temperature operation is allowed as long as the device maximum junction temperature is not exceeded.
(2) Differential input voltage V
ID
is defined as | IN+ – IN– |.
over operating free-air temperature range (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP
(1)
MAX UNIT
DIFFERENTIAL INPUTS
Positive going differential
V
IT+
50 mV
input high threshold
Negative going differential
V
IT–
–50 mV
input low threshold
A
(EQ)
Equalizer gain From 375 MHz to 1.875 GHz 5 dB
Termination resistance,
R
T(D)
80 100 120 Ω
differential
Open-circuit Input voltage
V
BB
AC-coupled inputs 1.6 V
(input self-bias voltage)
Biasing network dc
R
(BBDC)
30 k Ω
impedance
375 MHz 42
Biasing network ac
R
(BBAC)
Ω
impedance
1.875 GHz 8.4
DIFFERENTIAL OUTPUTS
V
OH
High-level output voltage R
L
= 100 Ω ±1%, 650 mVpp
PRES_1 = PRES_0=0;
V
OL
Low-level output voltage –650 mVpp
PREL_1 = PREL_0=0; 4 Gbps alternating
Output differential voltage
1010-pattern;
V
ODB(PP)
1000 1300 1500 mVpp
without preemphasis
(2)
Figure 1
V
OCM
Output common mode voltage 1.65 V
Change in steady-state
See Figure 6
∆ V
OC(SS)
common-mode output voltage 1 mV
between logic states
(1) All typical values are at T
A
= 25°C and V
CC
= 3.3 V supply unless otherwise noted. They are for reference purposes and are not
production tested.
(2) Differential output voltage V
(ODB)
is defined as | OUT+ – OUT– |.
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V
ODB(PP)
V
ODPE(PP)
SWITCHING CHARACTERISTICS
SN65LVCP40
SLLS623D – SEPTEMBER 2004 – REVISED FEBRUARY 2006
ELECTRICAL CHARACTERISTICS (continued)
over operating free-air temperature range (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP
(1)
MAX UNIT
Output preemphasis voltage PREx_1:PREx_0 = 00 0
ratio,
PREx_1:PREx_0 = 01 3
RL = 100 Ω ±1%;
V
(PE)
x = L or S; dB
PREx_1:PREx_0 = 10 6
See Figure 1
PREx_1:PREx_0 = 11 9
Output preemphasis is set to 9 dB during test
Preemphasis duration PREx_x = 1;
t
(PRE)
175 ps
measurement Measured with a 100-MHz clock signal;
R
L
= 100 Ω , ±1%, See Figure 2
Differential on-chip termination between OUT+ and
r
o
Output resistance 100 Ω
OUT–
CONTROL INPUTS
I
IH
High-level Input current VIN = VCC 5 µA
I
IL
Low-level Input currentn VIN = GND 90 125 µA
R
(PU)
Pullup resistance 35 k Ω
POWER CONSUMPTION
P
D
Device power dissipation All outputs terminated 100 Ω 650 880 mW
All outputs
I
CC
Device current consumption PRBS 2
7-1
pattern at 4 Gbps 254 mA
terminated 100 Ω
over operating free-air temperature range (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP
(1)
MAX UNIT
MULTIPLEXER
t
(SM)
Multiplexer switch time Multiplexer or loopback control to valid output 3 6 ns
DIFFERENTIAL OUTPUTS
Low-to-high propagation
t
PLH
0.5 1 ns
delay
Propagation delay input to output
See Figure 4
High-to-low propagation
t
PHL
0.5 1 ns
delay
t
r
Rise time 80 ps
20% to 80% of V
O(DB)
; Test Pattern: 100-MHz clock signal;
See Figure 3 and Figure 7
t
f
Fall time 80 ps
t
sk(p)
Pulse skew, | t
PHL
– t
PLH
|
(2)
20 ps
t
sk(o)
Output skew
(3)
All outputs terminated with 100 Ω 25 200 ps
t
sk(pp)
Part-to-part skew
(4)
500 ps
See Figure 7 for test circuit.
RJ Device random jitter, rms BERT setting 10
–15
0.8 2 ps-rms
Alternating 10-pattern.
(1) All typical values are at 25°C and with 3.3 V supply unless otherwise noted.
(2) t
sk(p)
is the magnitude of the time difference between the t
PLH
and t
PHL
of any output of a single device.
(3) t
sk(o)
is the magnitude of the time difference between the t
PLH
and t
PHL
of any two outputs of a single device.
(4) t
sk(pp)
is the magnitude of the difference in propagation delay times between any specified terminals of two devices when both devices
operate with the same supply voltages, at the same temperature, and have identical packages and test circuits.
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PIN ASSIGNMENTS
5
11
2
8
41
44
38
1
13
+
−
+
−
+
−
29
32
26
25
35
36
17
20
14
23
24
34
33
30
31
+
−
+
−
+
−
45
46
+
−
+
−
+
−
27
28
43
42
21
22
+
−
+
−
+
−
40
39
19
18
16
15
+
−
+
−
+
−
10
9
6
7
+
−
+
−
+
−
3
4
12
37
48
47
PREL_1
VCC
SOB_0N
SOB_0P
GND
LI_0P
LI_0N
VCC
LO_1P
LO_1N
GND
PREL_0
MUX_S1
VCC
SIA_1N
SIA_1P
GND
SIB_1N
SIB_1P
VCC
SOA_1N
SOA_1P
LB1A
LB1B
LB0B
LB0A
SOA_0P
SOA_0N
VCC
SIB_0P
SIB_0N
GND
SIA_0P
SIA_0N
VCC
MUX_S0
PRES_0
VCC
LO_0N
LO_0P
GND
LI_1N
LI_1P
VCC
SOB_1P
SOB_1N
REXT
PRES_1
SN65LVCP40
SLLS623D – SEPTEMBER 2004 – REVISED FEBRUARY 2006
SWITCHING CHARACTERISTICS (continued)
over operating free-air temperature range (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP
(1)
MAX UNIT
0 dB preemphasis
Intrinsic deterministic device (PREx_x = 0); PRBS 2
7-1
4 Gbps 30 ps
jitter
(5) (6)
, peak-to-peak See Figure 7 for the test pattern
circuit.
1.25 Gbps
Over 20-inch 7
DJ
FR4 trace
0 dB preemphasis
Absolute deterministic (PREx_x = 0); PRBS 2
7-1
4 Gbps
ps
output jitter
(7)
, peak-to-peak See Figure 7 for the test pattern
Over FR4
circuit.
trace 2-inch 20
to 20 inches
long
(5) Intrinsic deterministic device jitter is a measurement of the deterministic jitter contribution from the device. It is derived by the equation
(DJ
(OUT)
– DJ
(IN)
), where DJ
(OUT)
is the total peak-to-peak deterministic jitter measured at the output of the device in pspp. DJ
(IN)
is the
peak-to-peak deterministic jitter of the pattern generator driving the device.
(6) The SN65LVCP40 built-in passive input equalizer compensates for ISI. For a 20-inch FR4 transmission line with 8-mil trace width, the
LVCP40 typically reduces jitter by 60 ps from the device input to the device output.
(7) Absolute deterministic output jitter reflects the deterministic jitter measured at the SN65LVCP40 output. The value is a real measured
value with a Bit error tester as described in Figure 7 . The absolute DJ reflects the sum of all deterministic jitter components accumulated
over the link: DJ
(absolute)
= DJ
(Signal generator)
+ DJ
(transmission line)
+ DJ
(intrinsic(LVCP40))
.
5
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