TI-TPS23757.pdf资源-CSDN文库

需积分: 10 144 浏览量 2022-11-16 23:22:28 上传评论 5 收藏 1.47MB PDF 举报

资源详情

资源评论

Optional

Interface

OUT2

VC1

GATE

RTN, COM

ARTN

CTL

58V

0.1 Fm

DEN

FromEthernet

Pairs1,2

CTL

FromEthernet

Pairs3,4

CLS

DEN

FRS

APb

CLS

APb_OUT

Adapter

Presentand

Converter

Running

FRS

FBU

FBL

TLV431

OUT

GAT2

APb

APD2

APD1

PPD

Adapter

BLNK

APD

BLNK

DD1

OUT1

OUT

APb_OUT

TPS23757

www.ti.com

SLVS948D –JULY 2009–REVISED NOVEMBER 2013

High Efficiency PoE Interface and DC/DC Controller

The TPS23757 supports a number of input voltage

FEATURES

ORing options including highest voltage, external

• Powers up to 13 W (Input) PDs

adapter preference, and PoE preference.

• Legacy and IEEE 802.3at Type 1 PDs

The TPS23757 has an output flag indicating if an

• Optimized for Isolated DC/DC Converters

external wall adapter is active when used in

• Supports High-Efficiency Topologies

conjunction with ORing controls. The detection

signature pin can also be used to force power from

• Complete PoE Interface

the PoE source off. Classification can be

• Adapter ORing Support

programmed to any of the defined types with a single

• Programmable Frequency with Synch.

resistor.

• Robust 100 V, 0.5 Ω Hotswap MOSFET

The dc/dc controller features two complementary gate

• Pin Compatible with TPS23754/6

drivers with programmable dead time. This simplifies

design of highly-efficient flyback topologies or active-

• –40°C to 125°C Junction Temperature Range

clamp forward or flyback converters. The second gate

• Industry Standard TSSOP-20

driver may be disabled if desired for single MOSFET

topologies. The controller also features internal

APPLICATIONS

softstart, bootstrap startup source, current-mode

compensation, and a 78% maximum duty cycle. A

• IEEE 802.3at Type 1 Compliant Devices

programmable and synchronizable oscillator allows

• Video and VoIP Telephones

design optimization for efficiency and eases use of

• Access Points

the controller to upgrade existing power supply

designs. Accurate programmable blanking, with a

• Security Cameras

default period, simplifies the usual current- sense

filter design trade-offs.

DESCRIPTION

The TPS23757 is a combined Power over Ethernet The TPS23757 has a 9 V converter startup,

(PoE) powered device (PD) interface and current- permitting operation with 12 V wall adapters.

mode dc/dc controller optimized specifically for

isolated converters. The PoE interface supports the

IEEE 802.3at standard for a type 1 PD, which is

equivalent to the 13W standard of IEEE 802.3-2008.

Figure 1. High Efficiency Converter Using TPS23757

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of

Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

PRODUCTION DATA information is current as of publication date.

Products conform to specifications per the terms of the Texas

Instruments standard warranty. Production processing does not

necessarily include testing of all parameters.

TPS23757

SLVS948D –JULY 2009–REVISED NOVEMBER 2013

www.ti.com

This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with

appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.

ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more

susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.

PRODUCT INFORMATION

(1)

POE UVLO CONVERTER UVLO PoE Current

DUTY

STATUS ON / HYST. ON / HYST. Limit PACKAGE MARKING

CYCLE

(V) (V) (mA)

TPS23757PW Preview 0–78% 35/4.5 9 / 3.5 465 TSSOP-20 TPS23757

(1) For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI

web site at www.ti.com.

ABSOLUTE MAXIMUM RATINGS

(1) (2)

Voltage with respect to V

unless otherwise noted.

MIN MAX UNIT

ARTN

(2)

, COM

(2)

, DEN, PPD, RTN

(3)

–0.3 100 V

, V

DD1

CLS

(4)

-0.3 6.5 V

[APD, BLNK

(4)

, CTL, DT

(4)

, FRS

(4)

–0.3 6.5 V

(4)

] to [ARTN, COM]

Input voltage

CS to [ARTN,COM] –0.3 V

[ARTN, COM] to RTN –2 2 V

, APb, to [ARTN, COM] –0.3 19 V

GATE

(4)

, GAT2

(4)

to [ARTN, COM] –0.3 V

+0.3 V

Sinking current RTN Internally limited mA

Sourcing current V

Internally limited mA

Average Sourcing or sinking current GATE, GAT2 25 mArms

Human Body Model (HBM) 2 kV

Electrostatic Discharge Charge Device Model (CDM) 500 V

System level (contact/air) at RJ-45

(5)

8 / 15 kV

Operating junction temperature range T

–40 Internally limited °C

(1) Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings

only and functional operation of the device at these or any other conditions beyond those indicated under recommended operating

conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

(2) ARTN and COM typically tied to RTN.

(3) I

RTN

= 0 for V

RTN

> 80V.

(4) Do not apply voltage to these pins

(5) ESD per EN61000-4-2. A power supply containing the TPS23757 was subjected to the highest test levels in the standard. See the ESD

section.

TPS23757

www.ti.com

SLVS948D –JULY 2009–REVISED NOVEMBER 2013

RECOMMENDED OPERATING CONDITIONS

(1)

Voltage with respect to V

(unless otherwise noted)

MIN NOM MAX UNIT

Input voltage range ARTN, COM, PPD, RTN, V

, V

DD1

0 57 V

Input voltage range APb, V

to [ARTN, COM] 0 18 V

Input voltage range APD, CTL to [ARTN, COM] 0 V

Input voltage range CS to [ARTN, COM] 0 2 V

I Continuous RTN current (T

≤ 125°C)

(2)

400 mA

Sourcing current, V

0 2.5 5 mA

C V

capacitance 0.08 μF

BLNK

0 350 kΩ

Synchronization pulse width input (when used) 25 ns

Operating junction temperature range –40 125 °C

(1) ARTN and COM tied to RTN.

(2) This is the minimum current-limit value. PDs should be designed for maximum currents below this value to provide for unit power-draw

tolerance. IEEE 802.3at type 1 and IEEE 802.3-2008 compliant devices should not draw average current greater than 350 mA, or their

class power.

DISSIPATION RATINGS

PACKAGE

°C/W

(1)

°C/W

(2)

°C/W

(3)

PWP (TSSOP-20) 0.7 / 0.45 135 74

(1) Thermal resistance junction to case top, low-k / high-k board, natural convection, T

= T

TOP

+ (Ψ

x P

). Use Ψ

to validate T

from

measurements.

(2) JEDEC method with low-k board (1 signal layer), natural convection.

(3) JEDEC method with high-k board (2 signal – 2 plane layers).

ELECTRICAL CHARACTERISTICS

Unless otherwise noted: CS=COM=APD=CTL=RTN=ARTN, GATE and GAT2 float, R

FRS

= 68.1 kΩ, R

BLNK

= 249 kΩ, DT = V

PPD = V

, APb open, C

= C

= 0.1 μF, R

DEN

= 24.9 kΩ, R

CLS

open, 0 V ≤ (V

, V

DD1

) ≤ 57 V, 0 V ≤ V

≤ 18 V,

–40°C ≤ T

≤ 125°C. Typical specifications are at 25°C.

CONTROLLER SECTION ONLY

= RTN and V

= V

DD1

] or [V

= RTN = V

], all voltages referred to [ARTN, COM] (unless otherwise

noted).

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

CUV

rising 8.7 9 9.3

UVLO V

CUVH

Hysteresis

(1)

3.3 3.5 3.7

Operating current V

= 12 V, CTL = V

, R

= 68.1 kΩ 0.7 0.92 1.2 mA

DD1

= 10.2 V, V

(0) = 0 V 50 85 175

Bootstrap startup time,

= 22 μF

DD1

= 35 V, V

(0) = 0 V 27 45 92

DD1

= 10.2 V, V

= 8.6 V 0.44 1.06 1.80

Startup current source - I

DD1

= 48 V, V

= 0 V 2.7 4.8 6.8

Voltage 6.5 V ≤ V

≤ 18 V, 0 ≤ I

≤ 5 mA 4.8 5.10 5.25 V

(1) The hysteresis tolerance tracks the rising threshold for a given device.

TPS23757

SLVS948D –JULY 2009–REVISED NOVEMBER 2013

www.ti.com

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

FRS

Switching frequency CTL = V

, measure GATE, R

FRS

= 68.1 kΩ 227 253 278 kHz

MAX

Duty cycle CTL= V

, measure GATE 76 78 80 %

SYNC

Synchronization Input threshold 2 2.2 2.4 V

CTL

ZDC

0% duty cycle threshold V

CTL

↓ until GATE stops 1.3 1.5 1.7 V

Softstart period Interval from switching start to V

CSMAX

1.9 3.9 6.2 ms

Input resistance 70 100 145 kΩ

BLNK

BLNK = RTN 35 55 78

Blanking delay

(In addition to t

)

BLNK

= 49.9 kΩ 38 55 70

CTL = V

, C

GATE

= 1 nF,

GAT2

= 1 nF, measure GATE, GAT2

DT1

= 24.9 kΩ, GAT2 ↑ to GATE ↑ 40 50 62.5

Dead time

DT2

See Figure 2 for t

DTx

definition R

= 24.9 kΩ, GATE ↓ to GAT2 ↓ 40 50 62.5

DT1

= 75 kΩ, GAT2 ↑ to GATE ↑ 120 150 188

DT2

= 75 kΩ, GATE ↓ to GAT2 ↓ 120 150 188

CSMAX

Maximum threshold voltage V

CTL

= V

, V

rising until GATE duty cycle drops 0.5 0.55 0.6 V

Turnoff delay V

= 0.65 V 24 40 70 ns

Internal slope compensation

SLOPE

Peak voltage at maximum duty cycle, referenced to CS 120 155 185 mV

voltage

Peak slope compensation

SL_EX

CTL

= V

, I

at maximum duty cycle 30 42 54 μA

current

Bias current (sourcing) DC component of I

1 2.5 4.3 μA

GATE

Source current V

CTL

= V

, V

= 12 V, GATE high, pulsed measurement 0.37 0.6 0.95 A

Sink current V

CTL

= V

, V

= 12 V, GATE low, pulsed measurement 0.7 1.0 1.4 A

GAT2

CTL

= V

, V

= 12 V, GAT2 high, R

= 24.9 kΩ, pulsed

Source current 0.37 0.6 0.95 A

measurement

CTL

= V

, V

= 12 V, GAT2 low, R

= 24.9 kΩ, pulsed

Sink current 0.7 1.0 1.4 A

measurement

APD / PPD

APDEN

APD

rising 1.43 1.5 1.57

APD threshold voltage V

APDH

Hysteresis

(2)

0.29 0.31 0.33

PPDEN

PPD

- V

VSS

rising, UVLO disable 1.45 1.55 1.65

PPDH

Hysteresis

(2)

0.29 0.31 0.33

PPD threshold voltage

PPD2

PPD

- V

VSS

rising, Class enable 7.4 8.3 9.2

PPD2H

Hysteresis

(2)

0.5 0.6 0.7

APD leakage current

= 12 V, V

APD

= V

1 μA

(source or sink)

PPD

PPD sink current V

PPD

-V

VSS

= 1.5 V 2.5 5 7.5 μA

THERMAL SHUTDOWN

Turnoff temperature T

rising 135 145 155 °C

Hysteresis

(3)

20 °C

(2) The hysteresis tolerance tracks the rising threshold for a given device.

(3) These parameters are provided for reference only, and do not constitute part of TI's published specifications for purposes of TI's product

warranty.

DT1

GATEGAT2

50%

DT2

time

TPS23757

www.ti.com

SLVS948D –JULY 2009–REVISED NOVEMBER 2013

ELECTRICAL CHARACTERISTICS – PoE AND CONTROL

= V

DD1

] or [V

DD1

= RTN], V

= RTN, COM = RTN = ARTN, all voltages referred to V

unless otherwise noted

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

DETECTION (DEN) (V

= V

DD1

= RTN = V

SUPPLY

positive)

Measure I

SUPPLY

Detection current V

= 1.6 V 62 64.3 66.5

μA

= 10 V 399 406 414

Detection bias current V

= 10 V, float DEN, measure I

SUPPLY

5.6 10 μA

PD_DIS

Hotswap disable threshold 3 4 5 V

DEN leakage current V

DEN

= V

= 57 V, float V

DD1

and RTN, measure I

DEN

0.1 5 μA

CLASSIFICATION (CLS) (V

= V

DD1

= RTN = V

SUPPLY

positive)

13 V ≤ V

≤ 21 V, Measure I

SUPPLY

CLS

= 1270 Ω 1.8 2.1 2.4

CLS

= 243 Ω 9.9 10.4 10.9

Classification current,

CLS

applies to both cycles

CLS

= 137 Ω 17.6 18.5 19.4

CLS

= 90.9 Ω 26.5 27.7 29.3

CLS

= 63.4 Ω 38.0 39.7 42

CL_ON

Regulator turns on, V

rising 11.2 11.9 12.6

Classification regulator lower

threshold

CL_H

Hysteresis

(1)

1.55 1.65 1.75

CU_OFF

Regulator turns off, V

rising 21 22 23

Classification regulator upper

threshold

CU_H

Hysteresis

(1)

0.5 0.75 1.0

Leakage current V

= 57 V, V

CLS

= 0 V, DEN = V

, measure I

CLS

1 μA

PASS DEVICE (RTN) (V

DD1

= RTN)

On resistance 0.25 0.43 0.8 Ω

Current limit V

RTN

= 1.5 V, V

= 48 V, pulsed measurement 400 465 535 mA

Inrush limit V

RTN

= 2 V, V

: 0 V → 48 V, pulsed measurement 100 140 180 mA

Foldback voltage threshold V

rising 11 12.3 13.6 V

UVLO

UVLO_R V

rising 33.9 35 36.1

UVLO threshold V

UVLO_H Hysteresis

(1)

4.4 4.55 4.76

APb V

= 12 V, float V

DD1

, V

= 48 V, ARTN = V

ON characteristic V

APD

= 2 V, CTL = ARTN, (V

APb

- V

ARTN

) = 0.6 V 2 mA

Leakage current V

APb

= 18 V, (V

APD

-V

ARTN

) = 0 V, (V

PPD

- V

VSS

) = 0 V 10 μA

APb

Delay From start of switching to APb active 5 9 15 ms

THERMAL SHUTDOWN

Turnoff temperature T

rising 135 145 155 °C

Hysteresis

(2)

20 °C

(1) The hysteresis tolerance tracks the rising threshold for a given device.

(2) These parameters are provided for reference only, and do not constitute part of TI's published specifications for purposes of TI's product

warranty.

Figure 2. GATE and GAT2 Timing and Phasing

剩余38页未读，继续阅读

评论收藏

内容反馈

TI-TPS23757.pdf

评论0

最新资源

TI-TPS23757.pdf

评论0

最新资源

相关推荐

TI-CD74HC4543.pdf

TI-PGA2505.pdf

TI-UCD3040.pdf

TI-SN75LVPE801.pdf

TI-LMH1226.pdf

TI-TPS2378.pdf

TI-TPS51216.pdf

TI-TPS23756.pdf

TI-TPS65951.pdf

TI-TPS63000.pdf

TI-LMH34400.pdf

TI-AFE5812.pdf

TI-LMH1981.pdf

TI-CSD96370Q5M.pdf

TI-TL16C550C.pdf

TI-TPS60213.pdf

TI-TPS2543.pdf

TI-TPS92660.pdf

TI-TPS25926.pdf

TI-TPS54372.pdf

TI-TPS1663.pdf

TI-TPS51116.pdf

TI-TPS658640.pdf

TI-TPS55289.pdf

TI-REF200.pdf

TI-TPS51100.pdf

TI-TPS3704.pdf

TI-TPS60230.pdf

TI-TPS2216.pdf

TI-TPS60231.pdf