+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Legal Partition Candidates ;
+--------------------------------------------------+-------+----------------+--------------+----------------+--------+-----------------+---------------+-----------------+-------+----------------+--------------+------------------+-------------------+
; Hierarchy ; Input ; Constant Input ; Unused Input ; Floating Input ; Output ; Constant Output ; Unused Output ; Floating Output ; Bidir ; Constant Bidir ; Unused Bidir ; Input only Bidir ; Output only Bidir ;
+--------------------------------------------------+-------+----------------+--------------+----------------+--------+-----------------+---------------+-----------------+-------+----------------+--------------+------------------+-------------------+
; rom_log_inst|altsyncram_component|auto_generated ; 9 ; 0 ; 0 ; 0 ; 8 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ;
; rom_log_inst ; 9 ; 0 ; 0 ; 0 ; 8 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ;
+--------------------------------------------------+-------+----------------+--------------+----------------+--------+-----------------+---------------+-----------------+-------+----------------+--------------+------------------+-------------------+
FPGA实现对数变换算法 （206个子文件） 
_info 13KB _info 8KB _info 7KB _info 6KB _info 5KB _info 3KB _info 2KB _vmake 29B _vmake 29B _vmake 29B _vmake 29B _vmake 29B _vmake 29B _vmake 29B log.vpr.ammdb 581B log.root_partition.cmp.ammdb 465B log.map.ammdb 138B log_run_msim_rtl_verilog.do.bak 2KB log.v.bak 2KB log_run_msim_rtl_verilog.do.bak1 0B log_run_msim_rtl_verilog.do.bak2 2KB log_run_msim_rtl_verilog.do.bak3 2KB log_run_msim_rtl_verilog.do.bak4 2KB log_run_msim_rtl_verilog.do.bak5 2KB log_run_msim_rtl_verilog.do.bak6 2KB
原始图.bmp 750KB 1.bmp 376KB 2.bmp 376KB 灰度图.bmp 376KB 对数变换图.bmp 376KB log.cmp.bpm 796B log.map.bpm 763B log.cmp.cdb 7KB log.rtlv_sg.cdb 5KB log.root_partition.cmp.cdb 5KB log.map.cdb 4KB log.root_partition.map.cdb 3KB log.sgdiff.cdb 3KB log.map_bb.cdb 2KB log.(5).cnf.cdb 2KB log.rtlv_sg_swap.cdb 2KB log.(3).cnf.cdb 2KB log.(1).cnf.cdb 2KB log.(0).cnf.cdb 2KB log.(2).cnf.cdb 1KB log.(4).cnf.cdb 1KB log.root_partition.map.hbdb.cdb 1KB log.root_partition.map.reg_db.cdb 209B logic_util_heursitic.dat 3KB log.db_info 155B log.db_info 155B log.tiscmp.slow_1200mv_85c.ddb 119KB log.tiscmp.slow_1200mv_0c.ddb 119KB log.tiscmp.fast_1200mv_0c.ddb 119KB log.tiscmp.fastest_slow_1200mv_0c.ddb 111KB log.tiscmp.fastest_slow_1200mv_85c.ddb 111KB log.asm_labs.ddb 7KB log.tis_db_list.ddb 250B log.pti_db_list.ddb 192B log.root_partition.cmp.dfp 33B log_run_msim_rtl_verilog.do 2KB log.done 26B log.root_partition.map.dpi 2KB log.quiproj.20032.rdr.flock 0B log.root_partition.map.hbdb.hb_info 46B log.pre_map.hdb 15KB log.rtlv.hdb 14KB log.root_partition.cmp.hdb 13KB log.sgdiff.hdb 13KB log.cmp.hdb 13KB log.map.hdb 12KB log.root_partition.map.hdb 12KB log.root_partition.map.hbdb.hdb 12KB log.map_bb.hdb 10KB log.(1).cnf.hdb 1KB log.(0).cnf.hdb 999B log.(2).cnf.hdb 804B log.(4).cnf.hdb 801B log.(5).cnf.hdb 686B log.(3).cnf.hdb 685B log.hier_info 6KB log.hif 2KB log.cycloneive_io_sim_cache.45um_ff_1200mv_0c_fast.hsd 729KB log.cycloneive_io_sim_cache.45um_ss_1200mv_0c_slow.hsd 728KB log.cycloneive_io_sim_cache.45um_ss_1200mv_85c_slow.hsd 723KB
log.lpc.html 822B log.cmp.idb 2KB modelsim.ini 91KB log.ipinfo 354B log.jdi 222B log.root_partition.map.kpt 367B log.map.kpt 364B log.cmp_merge.kpt 220B log.root_partition.cmp.kpt 218B log.cmp.kpt 215B log.cmp.logdb 16KB log.root_partition.cmp.logdb 4B log.map_bb.logdb 4B log.map.logdb 4B log_mif.m 959B共 206 条
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