LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
use ieee.std_logic_arith.all;
ENTITY fenpin IS
PORT(
CLK:IN STD_LOGIC;
B:OUT STD_LOGIC;
B1:OUT STD_LOGIC;
DA:OUT INTEGER RANGE 15000 DOWNTO 0;
DA12_d:OUT INTEGER RANGE 15000 DOWNTO 0
);
END fenpin;
ARCHITECTURE EXAM OF fenpin IS
SIGNAL CNT:INTEGER RANGE 127 DOWNTO 0;
SIGNAL FP:INTEGER RANGE 0 TO 19;
SIGNAL CLK1:STD_LOGIC;
SIGNAL CNT1:INTEGER RANGE 127 DOWNTO 0;
BEGIN
PROCESS(CLK)
BEGIN
IF CLK'EVENT AND CLK='1' THEN
IF FP=19 THEN FP<=0;
CLK1<=NOT CLK1;
IF CNT=127 THEN CNT<=0;
ELSE CNT<=CNT+1;
END IF;
ELSE
FP<=FP+1;
IF(FP=9) THEN CLK1<= NOT CLK1;END IF;
END IF;
END IF;
END PROCESS;
PROCESS(CNT)
BEGIN
CASE CNT IS
WHEN 0=>DA<=14000;WHEN 1=>DA<=13998;
WHEN 2=>DA<=13966;WHEN 3=>DA<=13924;
WHEN 4=>DA<=13865;WHEN 5=>DA<=13790;
WHEN 6=>DA<=13699; WHEN 7=>DA<=13591;
WHEN 8=>DA<=13467;WHEN 9=>DA<=13328;
WHEN 10=>DA<=13173;WHEN 11=>DA<=13004;