1.dds_vhdl.VHDL
2.reg10b，reg32b.vhdl
3.adder10b，adder32b.vhdl
4.sin_rom.mif
--%%%%%%%%%%% --- dds_vhdl---%%%%%%%%
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity dds_vhdl is
Port ( clk : in std_logic;
fword: in std_logic_vector(7 downto 0);
pword :in std_logic_vector(7 downto 0);
fout : out std_logic_vector(9 downto 0) );
end ;
architecture one of dds_vhdl is
component reg32b
port (
load: IN std_logic;
din: IN std_logic_VECTOR(31 downto 0);
dout: OUT std_logic_VECTOR(31 downto 0));
end component;
component reg10b
port (
load: IN std_logic;
din: IN std_logic_VECTOR(9 downto 0);
dout: OUT std_logic_VECTOR(9 downto 0));
end component;
component adder32b
port (
a : IN std_logic_VECTOR(31 downto 0);
b : IN std_logic_VECTOR(31 downto 0);
s : OUT std_logic_VECTOR(31 downto 0));
end component;
component adder10b
port (
a : IN std_logic_VECTOR(9 downto 0);
b : IN std_logic_VECTOR(9 downto 0);
