PIC32-int.rar_Pic32 interrupt_pic32_pic32 函数

/******************************************************************** * FileName: int_tbl_lipb.c * Dependencies: * Processor: PIC32 * Hardware: N/A * Assembler: N/A * Linker: N/A * Company: Microchip Technology Inc.. * * Software License Agreement: * The software supplied herewith by Microchip Technology Incorporated * (the “Company”) for its PICmicro® Microcontroller is intended and * supplied to you, the Company’s customer, for use solely and * exclusively on Microchip PICmicro Microcontroller products. The * software is owned by the Company and/or its supplier, and is * protected under applicable copyright laws. All rights are reserved. * Any use in violation of the foregoing restrictions may subject the * user to criminal sanctions under applicable laws, as well as to * civil liability for the breach of the terms and conditions of this * license. * * THIS SOFTWARE IS PROVIDED IN AN “AS IS” CONDITION. NO WARRANTIES, * WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING, BUT NOT LIMITED * TO, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A * PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. THE COMPANY SHALL NOT, * IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL OR * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. * * $Id:$ * $Name: $ ********************************************************************/ #include <peripheral/int.h> enum { SFR_REG, SFR_CLR, SFR_SET, SFR_INV }; typedef volatile unsigned int VUINT; typedef struct { VUINT *ifs; VUINT *iec; unsigned int mask; }INT_SCR_TBL_ENTRY; const INT_SCR_TBL_ENTRY __IntSrcTbl[] = { { &IFS0, &IEC0, _IFS0_CTIF_MASK }, // Core Timer Interrupt { &IFS0, &IEC0, _IFS0_CS0IF_MASK }, // Core Software Interrupt 0 { &IFS0, &IEC0, _IFS0_CS1IF_MASK }, // Core Software Interrupt 1 { &IFS0, &IEC0, _IFS0_INT0IF_MASK }, // External Interrupt 0 { &IFS0, &IEC0, _IFS0_INT1IF_MASK }, // External Interrupt 1 { &IFS0, &IEC0, _IFS0_INT2IF_MASK }, // External Interrrupt 2 { &IFS0, &IEC0, _IFS0_INT3IF_MASK }, // External Interrupt 3 { &IFS0, &IEC0, _IFS0_INT4IF_MASK }, // External Interupt 4 { &IFS0, &IEC0, _IFS0_T1IF_MASK }, // Timer 1 { &IFS0, &IEC0, _IFS0_T2IF_MASK }, // Timer 2 { &IFS0, &IEC0, _IFS0_T3IF_MASK }, // TImer 3 { &IFS0, &IEC0, _IFS0_T4IF_MASK }, // Timer 4 { &IFS0, &IEC0, _IFS0_T5IF_MASK }, // Timer 5 { &IFS0, &IEC0, _IFS0_IC1IF_MASK }, // Input Capture 1 { &IFS0, &IEC0, _IFS0_IC2IF_MASK }, // Input Capture 2 { &IFS0, &IEC0, _IFS0_IC3IF_MASK }, // Input Capture 3 { &IFS0, &IEC0, _IFS0_IC4IF_MASK }, // Input Capture 4 { &IFS0, &IEC0, _IFS0_IC5IF_MASK }, // Input Capture 5 { &IFS1, &IEC1, _IFS1_IC1EIF_MASK }, // Input Capture 1 { &IFS1, &IEC1, _IFS1_IC2EIF_MASK }, // Input Capture 2 { &IFS1, &IEC1, _IFS1_IC3EIF_MASK }, // Input Capture 3 { &IFS2, &IEC2, _IFS2_IC4EIF_MASK }, // Input Capture 4 { &IFS2, &IEC2, _IFS2_IC5EIF_MASK }, // Input Capture 5 { &IFS0, &IEC0, _IFS0_OC1IF_MASK }, // Output Capture 1 { &IFS0, &IEC0, _IFS0_OC2IF_MASK }, // Output Capture 2 { &IFS0, &IEC0, _IFS0_OC3IF_MASK }, // Output Capture 3 { &IFS0, &IEC0, _IFS0_OC4IF_MASK }, // Output Capture 4 { &IFS0, &IEC0, _IFS0_OC5IF_MASK }, // Output Capture 5 { &IFS1, &IEC1, _IFS1_CNIF_MASK }, // Input Change /********************************************************** * SPI channel definitions ***********************************************************/ #ifdef _SPI1 { &IFS0, &IEC0, (_IFS0_SPI1EIF_MASK | _IFS0_SPI1TXIF_MASK | _IFS0_SPI1RXIF_MASK) }, // SPI 1 #else { (VUINT *)0, (VUINT *)0, 0 }, #endif #ifdef _SPI2A { &IFS1, &IEC1, (_IFS1_SPI2AEIF_MASK | _IFS1_SPI2ARXIF_MASK | _IFS1_SPI2ATXIF_MASK) }, #else { (VUINT *)0, (VUINT *)0, 0 }, #endif #ifdef _SPI1A { &IFS0, &IEC0, (_IFS0_SPI1AEIF_MASK | _IFS0_SPI1ARXIF_MASK | _IFS0_SPI1ATXIF_MASK) }, #else { (VUINT *)0, (VUINT *)0, 0 }, #endif #ifdef _SPI3A { &IFS1, &IEC1, (_IFS1_SPI3AEIF_MASK | _IFS1_SPI3ARXIF_MASK | _IFS1_SPI3ATXIF_MASK) }, #else { (VUINT *)0, (VUINT *)0, 0 }, #endif /********************************************************** * SPI channel definitions Fault ***********************************************************/ #ifdef _SPI1 { &IFS0, &IEC0, _IFS0_SPI1EIF_MASK }, // SPI 1 Fault #else { (VUINT *)0, (VUINT *)0, 0 }, #endif #ifdef _SPI2A { &IFS1, &IEC1, _IFS1_SPI2AEIF_MASK }, #else { (VUINT *)0, (VUINT *)0, 0 }, #endif #ifdef _SPI1A { &IFS0, &IEC0, _IFS0_SPI1AEIF_MASK }, #else { (VUINT *)0, (VUINT *)0, 0 }, #endif #ifdef _SPI3A { &IFS1, &IEC1, _IFS1_SPI3AEIF_MASK }, #else { (VUINT *)0, (VUINT *)0, 0 }, #endif /********************************************************** * SPI channel definitions Tx ***********************************************************/ #ifdef _SPI1 { &IFS0, &IEC0, _IFS0_SPI1TXIF_MASK }, // SPI 1 Receive Done #else { (VUINT *)0, (VUINT *)0, 0 }, #endif #ifdef _SPI2A { &IFS1, &IEC1, _IFS1_SPI2ATXIF_MASK }, #else { (VUINT *)0, (VUINT *)0, 0 }, #endif #ifdef _SPI1A { &IFS0, &IEC0, _IFS0_SPI1ATXIF_MASK }, #else { (VUINT *)0, (VUINT *)0, 0 }, #endif #ifdef _SPI3A { &IFS1, &IEC1, _IFS1_SPI3ATXIF_MASK }, #else { (VUINT *)0, (VUINT *)0, 0 }, #endif /********************************************************** * SPI channel definitions Rx ***********************************************************/ #ifdef _SPI1 { &IFS0, &IEC0, _IFS0_SPI1RXIF_MASK }, // SPI 1 Transfer Done #else { (VUINT *)0, (VUINT *)0, 0 }, #endif #ifdef _SPI2A { &IFS1, &IEC1, _IFS1_SPI2ARXIF_MASK }, #else { (VUINT *)0, (VUINT *)0, 0 }, #endif #ifdef _SPI1A { &IFS0, &IEC0, _IFS0_SPI1ARXIF_MASK }, #else { (VUINT *)0, (VUINT *)0, 0 }, #endif #ifdef _SPI3A { &IFS1, &IEC1, _IFS1_SPI3ARXIF_MASK }, #else { (VUINT *)0, (VUINT *)0, 0 }, #endif /********************************************************** * I2C channel definitions ***********************************************************/ #ifdef _I2C1 { &IFS0, &IEC0, (_IFS0_I2C1BIF_MASK | _IFS0_I2C1SIF_MASK | _IFS0_I2C1MIF_MASK) }, // I2C1 #else { (VUINT *)0, (VUINT *)0, 0 }, #endif #ifdef _I2C2 { &IFS1, &IEC1, (_IFS1_I2C2BIF_MASK | _IFS1_I2C2SIF_MASK | _IFS1_I2C2MIF_MASK) }, // I2C2 #else { (VUINT *)0, (VUINT *)0, 0 }, #endif #ifdef _I2C1A #if defined(_IFS0_I2C1AEIF_MASK) && !defined(_IFS0_I2C1ABIF_MASK) #define _IFS0_I2C1ABIF_MASK _IFS0_I2C1AEIF_MASK #endif #if defined(_IFS0_I2C1ARXIF_MASK) && !defined(_IFS0_I2C1ASIF_MASK) #define _IFS0_I2C1ASIF_MASK _IFS0_I2C1ARXIF_MASK #endif #if defined(_IFS0_I2C1ATXIF_MASK) && !defined(_IFS0_I2C1AMIF_MASK) #define _IFS0_I2C1AMIF_MASK _IFS0_I2C1ATXIF_MASK #endif { &IFS0, &IEC0, (_IFS0_I2C1ABIF_MASK | _IFS0_I2C1ASIF_MASK | _IFS0_I2C1AMIF_MASK) }, #else { (VUINT *)0, (VUINT *)0, 0 }, #endif #ifdef _I2C2A { &IFS1, &IEC1, (_IFS1_I2C2AEIF_MASK | _IFS1_I2C2ARXIF_MASK | _IFS1_I2C2ATXIF_MASK) }, #else { (VUINT *)0, (VUINT *)0, 0 }, #endif #ifdef _I2C3A { &IFS1, &IEC1, (_IF