intctl-regs.rar_Before

#include <linux/interrupt.h> #include <linux/dmar.h> #include <linux/spinlock.h> #include <linux/slab.h> #include <linux/jiffies.h> #include <linux/hpet.h> #include <linux/pci.h> #include <linux/irq.h> #include <linux/intel-iommu.h> #include <linux/acpi.h> #include <asm/io_apic.h> #include <asm/smp.h> #include <asm/cpu.h> #include <asm/irq_remapping.h> #include <asm/pci-direct.h> #include <asm/msidef.h> #include "irq_remapping.h" struct ioapic_scope { struct intel_iommu *iommu; unsigned int id; unsigned int bus; /* PCI bus number */ unsigned int devfn; /* PCI devfn number */ }; struct hpet_scope { struct intel_iommu *iommu; u8 id; unsigned int bus; unsigned int devfn; }; #define IR_X2APIC_MODE(mode) (mode ? (1 << 11) : 0) #define IRTE_DEST(dest) ((x2apic_mode) ? dest : dest << 8) static struct ioapic_scope ir_ioapic[MAX_IO_APICS]; static struct hpet_scope ir_hpet[MAX_HPET_TBS]; /* * Lock ordering: * ->dmar_global_lock * ->irq_2_ir_lock * ->qi->q_lock * ->iommu->register_lock * Note: * intel_irq_remap_ops.{supported,prepare,enable,disable,reenable} are called * in single-threaded environment with interrupt disabled, so no need to tabke * the dmar_global_lock. */ static DEFINE_RAW_SPINLOCK(irq_2_ir_lock); static int __init parse_ioapics_under_ir(void); static struct irq_2_iommu *irq_2_iommu(unsigned int irq) { struct irq_cfg *cfg = irq_cfg(irq); return cfg ? &cfg->irq_2_iommu : NULL; } static int get_irte(int irq, struct irte *entry) { struct irq_2_iommu *irq_iommu = irq_2_iommu(irq); unsigned long flags; int index; if (!entry || !irq_iommu) return -1; raw_spin_lock_irqsave(&irq_2_ir_lock, flags); if (unlikely(!irq_iommu->iommu)) { raw_spin_unlock_irqrestore(&irq_2_ir_lock, flags); return -1; } index = irq_iommu->irte_index + irq_iommu->sub_handle; *entry = *(irq_iommu->iommu->ir_table->base + index); raw_spin_unlock_irqrestore(&irq_2_ir_lock, flags); return 0; } static int alloc_irte(struct intel_iommu *iommu, int irq, u16 count) { struct ir_table *table = iommu->ir_table; struct irq_2_iommu *irq_iommu = irq_2_iommu(irq); struct irq_cfg *cfg = irq_cfg(irq); unsigned int mask = 0; unsigned long flags; int index; if (!count || !irq_iommu) return -1; if (count > 1) { count = __roundup_pow_of_two(count); mask = ilog2(count); } if (mask > ecap_max_handle_mask(iommu->ecap)) { printk(KERN_ERR "Requested mask %x exceeds the max invalidation handle" " mask value %Lx\n", mask, ecap_max_handle_mask(iommu->ecap)); return -1; } raw_spin_lock_irqsave(&irq_2_ir_lock, flags); index = bitmap_find_free_region(table->bitmap, INTR_REMAP_TABLE_ENTRIES, mask); if (index < 0) { pr_warn("IR%d: can't allocate an IRTE\n", iommu->seq_id); } else { cfg->remapped = 1; irq_iommu->iommu = iommu; irq_iommu->irte_index = index; irq_iommu->sub_handle = 0; irq_iommu->irte_mask = mask; } raw_spin_unlock_irqrestore(&irq_2_ir_lock, flags); return index; } static int qi_flush_iec(struct intel_iommu *iommu, int index, int mask) { struct qi_desc desc; desc.low = QI_IEC_IIDEX(index) | QI_IEC_TYPE | QI_IEC_IM(mask) | QI_IEC_SELECTIVE; desc.high = 0; return qi_submit_sync(&desc, iommu); } static int map_irq_to_irte_handle(int irq, u16 *sub_handle) { struct irq_2_iommu *irq_iommu = irq_2_iommu(irq); unsigned long flags; int index; if (!irq_iommu) return -1; raw_spin_lock_irqsave(&irq_2_ir_lock, flags); *sub_handle = irq_iommu->sub_handle; index = irq_iommu->irte_index; raw_spin_unlock_irqrestore(&irq_2_ir_lock, flags); return index; } static int set_irte_irq(int irq, struct intel_iommu *iommu, u16 index, u16 subhandle) { struct irq_2_iommu *irq_iommu = irq_2_iommu(irq); struct irq_cfg *cfg = irq_cfg(irq); unsigned long flags; if (!irq_iommu) return -1; raw_spin_lock_irqsave(&irq_2_ir_lock, flags); cfg->remapped = 1; irq_iommu->iommu = iommu; irq_iommu->irte_index = index; irq_iommu->sub_handle = subhandle; irq_iommu->irte_mask = 0; raw_spin_unlock_irqrestore(&irq_2_ir_lock, flags); return 0; } static int modify_irte(int irq, struct irte *irte_modified) { struct irq_2_iommu *irq_iommu = irq_2_iommu(irq); struct intel_iommu *iommu; unsigned long flags; struct irte *irte; int rc, index; if (!irq_iommu) return -1; raw_spin_lock_irqsave(&irq_2_ir_lock, flags); iommu = irq_iommu->iommu; index = irq_iommu->irte_index + irq_iommu->sub_handle; irte = &iommu->ir_table->base[index]; set_64bit(&irte->low, irte_modified->low); set_64bit(&irte->high, irte_modified->high); __iommu_flush_cache(iommu, irte, sizeof(*irte)); rc = qi_flush_iec(iommu, index, 0); raw_spin_unlock_irqrestore(&irq_2_ir_lock, flags); return rc; } static struct intel_iommu *map_hpet_to_ir(u8 hpet_id) { int i; for (i = 0; i < MAX_HPET_TBS; i++) if (ir_hpet[i].id == hpet_id && ir_hpet[i].iommu) return ir_hpet[i].iommu; return NULL; } static struct intel_iommu *map_ioapic_to_ir(int apic) { int i; for (i = 0; i < MAX_IO_APICS; i++) if (ir_ioapic[i].id == apic && ir_ioapic[i].iommu) return ir_ioapic[i].iommu; return NULL; } static struct intel_iommu *map_dev_to_ir(struct pci_dev *dev) { struct dmar_drhd_unit *drhd; drhd = dmar_find_matched_drhd_unit(dev); if (!drhd) return NULL; return drhd->iommu; } static int clear_entries(struct irq_2_iommu *irq_iommu) { struct irte *start, *entry, *end; struct intel_iommu *iommu; int index; if (irq_iommu->sub_handle) return 0; iommu = irq_iommu->iommu; index = irq_iommu->irte_index + irq_iommu->sub_handle; start = iommu->ir_table->base + index; end = start + (1 << irq_iommu->irte_mask); for (entry = start; entry < end; entry++) { set_64bit(&entry->low, 0); set_64bit(&entry->high, 0); } bitmap_release_region(iommu->ir_table->bitmap, index, irq_iommu->irte_mask); return qi_flush_iec(iommu, index, irq_iommu->irte_mask); } static int free_irte(int irq) { struct irq_2_iommu *irq_iommu = irq_2_iommu(irq); unsigned long flags; int rc; if (!irq_iommu) return -1; raw_spin_lock_irqsave(&irq_2_ir_lock, flags); rc = clear_entries(irq_iommu); irq_iommu->iommu = NULL; irq_iommu->irte_index = 0; irq_iommu->sub_handle = 0; irq_iommu->irte_mask = 0; raw_spin_unlock_irqrestore(&irq_2_ir_lock, flags); return rc; } /* * source validation type */ #define SVT_NO_VERIFY 0x0 /* no verification is required */ #define SVT_VERIFY_SID_SQ 0x1 /* verify using SID and SQ fields */ #define SVT_VERIFY_BUS 0x2 /* verify bus of request-id */ /* * source-id qualifier */ #define SQ_ALL_16 0x0 /* verify all 16 bits of request-id */ #define SQ_13_IGNORE_1 0x1 /* verify most significant 13 bits, ignore * the third least significant bit */ #define SQ_13_IGNORE_2 0x2 /* verify most significant 13 bits, ignore * the second and third least significant bits */ #define SQ_13_IGNORE_3 0x3 /* verify most significant 13 bits, ignore * the least three significant bits */ /* * set SVT, SQ and SID fields of irte to verify * source ids of interrupt requests */ static void set_irte_sid(struct irte *irte, unsigned int svt, unsigned int sq, unsigned int sid) { if (disable_sourceid_checking) svt = SVT_NO_VERIFY; irte->svt = svt; irte->sq = sq; irte->sid = sid; } static int set_ioapic_sid(struct irte *irte, int apic) { int i; u16 sid = 0; if (!irte) return -1; down_read(&dmar_global_lock); for (i = 0; i < MAX_IO_APICS; i++) { if (ir_ioapic[i].iommu && ir_ioapic[i].id == apic) { sid = (ir_ioapic[i].bus << 8) | ir_ioapic[i].devfn; break; } } up_read(&dmar_global_lock); if (sid == 0) { pr_warning("Failed to set source-id of IOAPIC (%d)\n", apic); return -1; } set_irte_sid(irte, SVT_VERIFY_SID_SQ, SQ_ALL_16, sid); return 0; } static int set_hpet_sid(struct irte *irte, u8 id) { int i; u16 sid = 0; if (!irte) return -1; down_read(&dmar_global_lock); for (i = 0; i