vhdl.rar_7人表决

library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_arith.all; use ieee.std_logic_unsigned.all; entity s_detect is port(data,clk:in std_logic; y: out std_logic); end s_detect; architecture behav of s_detect is type state is(s0,s1,s2,s3,s4,s5,s6,s7,s8,s9,s10,s11,s12,s13,s14,s15,s16); signal p: state; signal n:state; begin process(clk) begin if clk'event and clk='1' then p<=n; end if; end process; process(data,p) begin case p is when s0=>if data='1' then n<=s1; else n<=s0; end if; y<='0'; when s1=>if data='1' then n<=s2; else n<=s0; end if; y<='0'; when s2=>if data='1' then n<=s3; else n<=s0; end if; y<='0'; when s3=>if data='1' then n<=s4; else n<=s0; end if; y<='0'; when s4=>if data='1' then n<=s5; else n<=s0; end if; y<='0'; when s5=>if data='1' then n<=s6; else n<=s0; end if; y<='0'; when s6=>if data='1' then n<=s7; else n<=s0; end if; y<='0'; when s7=>if data='1' then n<=s8; else n<=s0; end if; y<='0'; when s8=>if data='0' then n<=s9; else n<=s0; end if; y<='0'; when s9=>if data='1' then n<=s10; else n<=s0; end if; y<='0'; when s10=>if data='1' then n<=s11; else n<=s0; end if; y<='0'; when s11=>if data='1' then n<=s12; else n<=s0; end if; y<='0'; when s12=>if data='1' then n<=s13; else n<=s0; end if; y<='0'; when s13=>if data='1' then n<=s14; else n<=s0; end if; y<='0'; when s14=>if data='1' then n<=s15; else n<=s0; end if; y<='0'; when s15=>if data='0' then n<=s16; else n<=s0; end if; y<='0'; when s16=>n<=s0; y<='1'; when others=>null; end case; end process; end behav;