vhdl.rar_三人表决器

--三人表决器（三种不同的描述方式） vhdl -- Three-input Majority Voter -- The entity declaration is followed by three alternative architectures which achieve the same functionality in different ways. ENTITY maj IS PORT(a,b,c : IN BIT; m : OUT BIT); END maj; --Dataflow style architecture ARCHITECTURE concurrent OF maj IS BEGIN --selected signal assignment statement (concurrent) WITH a&b&c SELECT m <= '1' WHEN "110"|"101"|"011"|"111",'0' WHEN OTHERS; END concurrent; --Structural style architecture ARCHITECTURE structure OF maj IS --declare components used in architecture COMPONENT and2 PORT(in1, in2 : IN BIT; out1 : OUT BIT); END COMPONENT; COMPONENT or3 PORT(in1, in2, in3 : IN BIT; out1 : OUT BIT); END COMPONENT; --declare local signals SIGNAL w1, w2, w3 : BIT; BEGIN --component instantiation statements. --ports of component are mapped to signals --within architecture by position. gate1 : and2 PORT MAP (a, b, w1); gate2 : and2 PORT MAP (b, c, w2); gate3 : and2 PORT MAP (a, c, w3); gate4 : or3 PORT MAP (w1, w2, w3, m); END structure; --Behavioural style architecture using a look-up table ARCHITECTURE using_table OF maj IS BEGIN PROCESS(a,b,c) CONSTANT lookuptable : BIT_VECTOR(0 TO 7) := "00010111"; VARIABLE index : NATURAL; BEGIN index := 0; --index must be cleared each time process executes IF a = '1' THEN index := index + 1; END IF; IF b = '1' THEN index := index + 2; END IF; IF c = '1' THEN index := index + 4; END IF; m <= lookuptable(index); END PROCESS; END using_table; 通用寄存器 vhdl -- Universal Register -- This design is a universal register which can be used as a straightforward storage register, a bi-directional shift register, an up counter and a down counter. -- The register can be loaded from a set of parallel data inputs and the mode is controlled by a 3-bit input. -- The 'termcnt' (terminal count) output goes high when the register contains zero. LIBRARY ieee; USE ieee.Std_logic_1164.ALL; USE ieee.Std_logic_unsigned.ALL; ENTITY unicntr IS GENERIC(n : Positive := 8); --size of counter/shifter PORT(clock, serinl, serinr : IN Std_logic; --serial inputs mode : IN Std_logic_vector(2 DOWNTO 0); --mode control datain : IN Std_logic_vector((n-1) DOWNTO 0); --parallel inputs dataout : OUT Std_logic_vector((n-1) DOWNTO 0); --parallel outputs termcnt : OUT Std_logic); --terminal count output END unicntr; ARCHITECTURE v1 OF unicntr IS SIGNAL int_reg : Std_logic_vector((n-1) DOWNTO 0); BEGIN main_proc : PROCESS BEGIN WAIT UNTIL rising_edge(clock); CASE mode IS --reset WHEN "000" => int_reg <= (OTHERS => '0'); --parallel load WHEN "001" => int_reg <= datain; --count up WHEN "010" => int_reg <= int_reg + 1; --count down WHEN "011" => int_reg <= int_reg - 1; --shift left WHEN "100" => int_reg <= int_reg((n-2) DOWNTO 0) & serinl; --shift right WHEN "101" => int_reg <= serinr & int_reg((n-1) DOWNTO 1); --do nothing WHEN OTHERS => NULL; END CASE; END PROCESS; det_zero : PROCESS(int_reg) --detects when count is 0 BEGIN termcnt <= '1'; FOR i IN int_reg'Range LOOP IF int_reg(i) = '1' THEN termcnt <= '0'; EXIT; END IF; END LOOP; END PROCESS; --connect internal register to dataout port dataout <= int_reg; END v1;