library ieee ;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all ;
entity jianpan is
port(
clk: in std_logic ; --100mhz ==0.01us 1us 100
col: in std_logic_vector(3 downto 0);
row: out std_logic_vector(3 downto 0);
wei: out std_logic_vector(2 downto 0);
duan: out std_logic_vector(7 downto 0)
);
end ;
architecture a of jianpan is
signal count : std_logic_vector(16 downto 0);
signal wei_s : std_logic_vector(2 downto 0);
signal t : std_logic_vector(5 downto 0);
signal flag : std_logic;
signal num0 : std_logic_vector(4 downto 0);-- integer;
signal num1 : std_logic_vector(4 downto 0);-- integer;
signal num2 : std_logic_vector(4 downto 0);-- integer;
signal num3 : std_logic_vector(4 downto 0);-- integer;
signal num4 : std_logic_vector(4 downto 0);-- integer;
signal num5 : std_logic_vector(4 downto 0);-- integer;
signal num6 : std_logic_vector(4 downto 0);-- integer;
signal num7 : std_logic_vector(4 downto 0);-- integer;
signal num8 : std_logic_vector(4 downto 0);-- integer;
signal duan_s : std_logic_vector(4 downto 0);-- integer;
signal old_num : std_logic_vector(4 downto 0);-- integer;
signal p_num : std_logic_vector(4 downto 0);-- integer;
signal state : std_logic_vector(4 downto 0);-- integer;
begin
process(clk)
begin
if clk'event and clk = '1' then
count<=count+1;
if count = "11000011010100000" then
count <= (others=>'0');
end if;
end if;
end process ;
