/*
*-----------------------------------------------------------------------------
* The confidential and proprietary information contained in this file may
* only be used by a person authorised under and to the extent permitted
* by a subsisting licensing agreement from ARM Limited.
*
* (C) COPYRIGHT 2009-2010 ARM Limited.
* ALL RIGHTS RESERVED
*
* This entire notice must be reproduced on all copies of this file
* and copies of this file may only be made by a person if such person is
* permitted to do so under the terms of a subsisting license agreement
* from ARM Limited.
*
* SVN Information
*
*
* Revision : $Revision: 1.1 $
*
* Release information : cortexm4_r0p1_00rel0
*-----------------------------------------------------------------------------
*/
////////////////////////////////////////////////////////////////////////////////
//
// CortexM4 Integration Kit Debug Driver Block Code
//
////////////////////////////////////////////////////////////////////////////////
//
// This code always runs on the Cortex-M4 core within the debug driver
// module in the Integration Kit testbench.
//
// The debug driver uses the same verilog components (ROM, RAM, GPIO) and
// memory map as the CM4IKMCU. However, the debug driver uses a separate
// CMSIS device header file (cm4ikdebugdriver.h) to allow the MCU system
// to be modified by the end user without affecting the debug driver.
//
// This code provides access to various test routines that can use
// either a SerialWire or JTAG interface to connect to the
// CM4IKMCU. Some functions, such as QueryFirstCall(), do not use the
// Debug interface to the CM4IKMCU at all.
//
// The functions available to the CM4IKMCU are enumerated in IKtests.h
// by the variable "Function". These correspond to actual functions
// within this file beneath the comment "Functions Available to IK
// Core".
//
// Communication between the CM4IKMCU and the Debug Driver takes place
// in two ways:
//
// [1]
//
// Function Calling, Function completion and Error status use a simple
// handshake using GPIO0. Refer to the main() function in this file,
// and the functions CallDebugDriver(), StartDebugDriver() and
// CheckDebugDriver() in IKtests.c for details.
//
//
// [2]
//
// Some tests and functions need to pass more complex data between the
// CM4IKMCU and the debug driver. For these cases, an area of memory
// in the CM4IKMCU SRAM is predefined as an area for passing values
// between the debug driver and CM4IKMCU.
//
// The region used is the last 4 words of the CM4IKMCU SRAM.
// It is assumed that the CM4IKMCU initial stack pointer is set 4 words
// below the top of RAM. The debugdriver reads the CM4IKMCU vector table
// to determine its SP, and therefore the location of these four words.
//
// The debug driver accesses this region using
// CM4IKMCU.stacktop and suitable offsets. CM4IKMCU accesses this
// region using the array DEBUGDRIVERDATA, defined in IKtests.h
//
// Refer to test debug.c and function ConnectCheckHaltDbgrestart() for
// an example of how this memory region can be used.
//
//
#include "cm4ikdebugdriver.h" // CMSIS Support for the DebugDriver
#include "debugdriver.h" // Local header file defining GPIO allocation etc
#include <stdio.h> // Access to printf
#include "IKtests.h" // Get Pin allocations for CM4IKMCU GPIOs
////////////////////////////////////////////////////////////////////////////////
//
// Macro definitions to generate SerialWire packet headers at compilation time
//
// Header Bits
#define AP 1
#define DP 0
#define READ 1
#define WRITE 0
// DP Register Addresses
#define DPIDR 0
#define ABORT 0
#define CTRLSTAT 0x4
#define DLCR 0x4
#define RESEND 0x8
#define SELECT 0x8
#define RDBUFF 0xc
// AP Register Addresses
#define CSW 0x00
#define TAR 0x04
#define DRW 0x0c
#define BD0 0x10
#define BD1 0x14
#define BD2 0x18
#define BD3 0x1c
#define CFG 0xf4
#define BASE 0xf8
#define IDR 0xfc
#define SW_HEADER_PARITY(APnDP,RnW,Address) ( (APnDP & 0x1) ^ (RnW & 0x1) ^ ((Address & 0x4) >> 2) ^ ((Address & 0x8) >> 3) )
// Start, APnDP, RnW, A[3:2], Parity, Stop, Park
#define SW_HEADER(APnDP,RnW,Address) (1 | ((APnDP & 0x1) << 1) | ((RnW & 0x1) << 2) | ((Address & 0xC) << 1) | SW_HEADER_PARITY(APnDP,RnW,Address) << 5 | 0 << 6 | 1 << 7)
// SW responses
#define SW_DP_ACK_OK 1
#define SW_DP_ACK_WAIT 2
#define SW_DP_ACK_FAULT 4
////////////////////////////////////////////////////////////////////////////////
//
// JTAG Definitions
//
#define JTAG_ABORT 0x8
#define JTAG_DPACC 0xa
#define JTAG_APACC 0xb
#define JTAG_IDCODE 0xe
#define JTAG_BYPASS 0xf
#define JTAG_SCAN(Address,RnW) (((Address & 0xC) >> 1) | RnW)
#define JTAG_DP_ACK_OKFAULT 2
#define JTAG_DP_ACK_WAIT 4
////////////////////////////////////////////////////////////////////////////////
//
// ARMv6M Debug register definitions
//
// DHCSR
#define DHCSR 0xE000EDF0
#define DBGKEY 0xA05F0000
#define S_LOCKUP (1UL << 19)
#define S_SLEEP (1UL << 18)
#define S_HALT (1UL << 17)
#define S_REGRDY (1UL << 16)
#define C_MASKINTS (1UL << 3)
#define C_STEP (1UL << 2)
#define C_HALT (1UL << 1)
#define C_DEBUGEN (1UL << 0)
// DCRSR
#define DCRSR 0xE000EDF4
#define REGWnR (1UL << 16)
#define R0 0x00
#define R1 0x01
#define R2 0x02
#define R3 0x03
#define R4 0x04
#define R5 0x05
#define R6 0x06
#define R7 0x07
#define R8 0x08
#define R9 0x09
#define R10 0x0A
#define R11 0x0B
#define R12 0x0C
#define SP 0x0D
#define LR 0x0E
#define DebugReturnAddress 0x0F
#define xPSR 0x10
#define MSP 0x11
#define PSP 0x12
#define CONTROL 0x14
// DCRDR
#define DCRDR 0xE000EDF8
////////////////////////////////////////////////////////////////////////////////
//
// CM4IKMCU GPIO Access
//
// Some functions in the debug driver need to access peripherals in the
// CM4IKMCU memory map. If the components or memory map of CM4IKMCU is modified,
// the following definition may also need to be updated.
//
#define MCU_GPIO1(mask,byte) (uint32_t)(0x40000800 | (mask << 2) | byte)
////////////////////////////////////////////////////////////////////////////////
//
// Function Prototypes
//
// SerialWire
uint32_t SWConnect(void);
uint32_t SWHeader(uint8_t);
uint32_t SWDataRead(void);
void SWDataWrite(uint32_t);
void SerialWireClockOut (uint32_t, uint32_t);
uint32_t SerialWireClockIn (uint32_t);
// JTAG
void JTAGTransition(uint32_t, uint8_t);
uint64_t JTAGShift(uint64_t, uint8_t);
uint64_t JTAGScanIDCODE(void);
void JTAGScanIR(uint32_t);
uint64_t JTAGScanDR(uint64_t);
// Wire Protocol Agnostic functions
void InitCommRegion(void);
uint32_t SwapEndian(uint32_t);
uint32_t ReadMem(uint32_t);
uint32_t ReadMemH(uint32_t);
uint32_t ReadMemB(uint32_t);
void WriteMem(uint32_t, uint32_t);
void WriteMemH(uint32_t, uint32_t);
void WriteMemB(uint32_t, uint32_t);
void JtagAPnDP(uint32_t);
void DPWriteBANKSEL(uint32_t);
void DPWriteCTRLSTAT(uint32_t);
uint32_t DPReadCTRLSTAT(void);
void APWriteCSW(uint32_t);
void APWriteTAR(uint32_t);
uint32_t APReadDRW(void);
void APWriteDRW(uint32_t);
uint32_t DPReadRDBUFF(void);
uint32_t DPReadIDR(void);
uint32_t APReadIDR(void);
uint32_t APReadBASE(void);
void DPClearSTICKYERR(void);
uint32_t DDCheck(char *, uint32_t, uint32_t);
// Prototypes for IK exposed functions
uint32_t CheckOK(void);
uint32_t Delay(void);
uint32_t SetModeJTAG(void);
uint32_t SetModeSW(void);
uint32_t CheckTAPID(void);
uint32_t CheckDPIDR(void);
uint32_t DAPPowerUp(void);
uint32_t DAPPowerDown(void);
uint32_t CheckAPIDR(void);
uint32_t CheckBASE(void);
uint32_t CheckCPUID(void);
uint32_t CheckROMTable(void);
uint32_t CheckNumBKPT(void);
uint32_t CheckNumWPT(void);
uint32_t CheckROMPID3(void);
uint32_t CheckSCSPID3(void);
uint32_t CheckDWTPID3(void);
uint32_t CheckBPUPID3(void);
uint32_t GetMemValue(void);
uint32_t ConnectWakeUnhalt(void);
uint32_t QueryFirstCall(void);
uint32_t ConnectCheckUnlockup(void);
uint32_t EnableHaltingD
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JTAG_SWD 驱动代码.rar_JTAG 驱动_c_inventedsaj_jtag代码_swd
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JTAG_SWD 驱动代码.rar_JTAG 驱动_c_inventedsaj_jtag代码_swd (173个子文件)
retarget_cm4ikmcu.__i 306B
system_cm4ikmcu.__i 298B
core_cm4.__i 285B
iktests.__i 266B
hellow.__i 262B
stackheap._ia 202B
bus_matrix.uvgui.Administrator 137KB
hellow.uvgui.Administrator 132KB
fpu.uvgui.Administrator 73KB
debugdriver.uvgui.Administrator 72KB
IntegrationKit.uvmpw.uvgui.Administrator 70KB
max_power.uvgui.Administrator 5KB
debug.uvgui.Administrator 5KB
mpu.uvgui.Administrator 5KB
romtable.uvgui.Administrator 5KB
interrupt.uvgui.Administrator 5KB
reset.uvgui.Administrator 5KB
itm_swo.uvgui.Administrator 5KB
itm_trace.uvgui.Administrator 5KB
sleep.uvgui.Administrator 5KB
dhry.uvgui.Administrator 5KB
etm_trace.uvgui.Administrator 5KB
speed_indicative.uvgui.Administrator 5KB
interrupt_priority.uvgui.Administrator 5KB
etm_swo.uvgui.Administrator 5KB
config_check.uvgui.Administrator 5KB
flash_patch.uvgui.Administrator 5KB
ahb_compliance_check.uvgui.Administrator 5KB
bus_matrix.axf 34KB
hellow.axf 27KB
hellow.uvgui_Administrator.bak 67KB
hellow_uvproj.bak 17KB
hellow_uvopt.bak 11KB
bus_matrix.bin 2KB
hellow.bin 2KB
debugdriver.c 65KB
config_check.c 22KB
core_cm4.c 17KB
dhry_1.c 14KB
max_power.c 12KB
etm_swo.c 12KB
speed_indicative.c 11KB
etm_trace.c 11KB
itm_trace.c 11KB
interrupt.c 10KB
mpu.c 9KB
romtable.c 9KB
itm_swo.c 9KB
debug.c 8KB
flash_patch.c 6KB
bus_matrix.c 5KB
dhry_2.c 5KB
boot.c 5KB
sleep.c 5KB
ahb_compliance_check.c 4KB
boot_debugdriver.c 4KB
fpu.c 4KB
interrupt_priority.c 4KB
IKtests.c 4KB
reset.c 3KB
retarget_cm4ikdebugdriver.c 2KB
retarget_cm4ikmcu.c 2KB
hellow.c 2KB
system_cm4ikdebugdriver.c 2KB
system_cm4ikmcu.c 2KB
simulator_mti.cmds 42B
simulator_nc.cmds 12B
simulator_vcs.cmds 6B
CM4IKMCU_integration.cpf 6KB
CM4IKMCU.cpf 6KB
boot.crf 37KB
retarget_cm4ikmcu.crf 36KB
bus_matrix.crf 36KB
hellow.crf 35KB
iktests.crf 31KB
system_cm4ikmcu.crf 25KB
core_cm4.crf 4KB
retarget_cm4ikmcu.d 535B
bus_matrix.d 418B
boot.d 392B
hellow.d 358B
iktests.d 313B
system_cm4ikmcu.d 253B
core_cm4.d 105B
stackheap.d 37B
bus_matrix_CM4IKMCU - Cortex-M4.dep 4KB
hellow_CM4IKMCU - Cortex-M4.dep 4KB
dsmdotcshrc 2KB
core_cm4.h 67KB
dhry.h 19KB
IKConfig.h 7KB
IKtests.h 7KB
cm4ikmcu.h 6KB
cm4ikdebugdriver.h 5KB
debugdriver.h 4KB
debugdriver_functions.h 2KB
system_cm4ikdebugdriver.h 1KB
system_cm4ikmcu.h 1KB
CMSIS_Core.htm 45KB
bus_matrix.htm 27KB
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