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ARM JTAG接口和SWD接口协议。ARM_debug_interface_v5
Copyright@ 2006 ARM Limited 110 Fulbourn Road Cambridge England cbl 9NJ Restricted Rights Legend: Use, duplication or disclosure by the United States government is subject to the restrictions set forth in DFARS 252.227-7013(c(1)(ii)and FAR 52.227-19 Figure 4-3 on page 4-5 reproduced with permission IEEE Std 1149.1-1990 IEEE Standard Test Access Port and Boundary Scan Architecture Copyright 2006, by IEEE. The ieee disclaims any responsibility or liability resulting from the placement and use in the described manner Confidentiality Status This document is Non-Confidential. The right to use, copy and disclose this document may be subject to license restrictions in accordance with the terms of the agreement entered into by arm and the party that arm delivered this document to Web address http://www.arm.com ARM IHI O031A Copyright o 2006 ARM Limited. All rights reserved. Copyright C 2006 ARM Limited. All rights reserved ARM IHI 0031A Contents ARM Debug Interface V5 Architecture Specification Preface About this specification XVIll Conventions XX Further reading XXII Feedback 面面面面面 XX l Chapter 1 Introduction About the ARM Debug Interface version5(ADlv5)…… 1.2 The function of the ARM Debug Interface The subdivisions of an ARM Debug Interface 1-5 Design choices for an ARM Debug Interface v5 implementation Chapter 2 Overview of the aRM debug Interface and its components 2.1 ARM Debug Interface overvie 2-2 2.2 The external interface, the debug port (dP) 2-3 The resource interface, the access ports(aps) .2-5 2.4 ARM Debug Interface implementation examples 2 Accessing Access Ports…… 2-8 ARM IHI O031A Copyright o 2006 ARM Limited. All rights reserved. Chapter 3 Common Debug Port(DP)features Sticky fla d dP error responses 3-2 3.2 Pushed compare and pushed verify operations 3-5 3.3 The transaction Counter 3-8 System and Debug power and Debug reset control……… 3-9 Chapter 4 The JTAG Debug Port JTAG-DP 4.1 The Debug TAP State Machine introduction 4-2 4.2 The scan chain interface 4-3 4.3 丨 R scan chain and ir instructions∴…4-8 DR scan chain and DR registers 4-12 Chapter 5 The Serial Wire Debug Port ( SW-DP 5.1 Introduction to the DAP Serial Wire Debug Port 5-2 5.2 Introduction to the ARM Serial Wire Debug(SWD) protocol 5-3 5.3 Serial Wire Debug protocol operation………….5-5 Protocol description 5-10 Chapter 6 Debug Port Registers 6.1 Debug Port registers overview 6-2 6.2 Debug Port(DP)register descriptions 6-6 Chapter 7 Common Access Port(AP)features Overview of Access Ports(APs) 7-2 7.2 The identification model for access ports 7-3 7.3 Selecting and accessing an AP 面面面面面 7-4 Chapter 8 The Memory Access Port (MEM-AP) 8.1 Overview of the function of a Memory Access Port (MEM-AP) 8-2 8.2 MEM-AP functions 8-8 8.3 MEM-AP examples of pushed verify and pushed compare 8-22 8.4 MEM-AP implementation requirements 8-24 Chapter 9 The JTAG Access Port (JTAG-AP 9.1 Overview of the function of a JTAG Access Port (JTAG-AP)....9-2 9.2 The TAG Engine Byte Command Protocol ∴9-10 Chapter 10 Access Port(AP)Registers Overview and the Common AP Register 10.1 Access Port(AP) registers overview 10-2 10.2 The common Access Port register, the IDR ∴10-3 Chapter 11 Memory Access Port( MEM-AP)Registers 11.1 Memory Access Port(MEM-AP)register summary 11-2 11.2 MEM-aP detailed register descriptions Copyright C 2006 ARM Limited. All rights reserved ARM IHI 0031A Chapter 12 JTAG Access Port (JTAG-AP)Registers 12.1 JTAG Access Port(JTAG-AP)register summary 12-2 12.2 JTAG-aP detailed register descriptions 12-5 Chapter 13 Component and Peripheral ID Registers 13.1 Component and Peripheral iD registers…………………132 13.2 The Component ID Registers 13-4 13.3 The Peripheral Id Registers 13-9 Chapter 14 ROM Tables 14.1 ROM Table overview 14-2 14.2 ROM Table entrⅰes∴ 14-5 14.3 The MEMTYPE Register 14-9 14.4 Component and Peripheral ID Registers 14-10 14.5 ROM Table hierarchies 14-12 Glossary ARM IHI O031A Copyright o 2006 ARM Limited. All rights reserved. Copyright C 2006 ARM Limited. All rights reserved ARM IHI 0031A List of tables ARM Debug Interface v5 Architecture Specification Change History… B国国国面面B面面面 Table 2-1 Comparison of IeEE 1149. 1 and JTAG DP naming Table 4-1 JTAG-DP signal connections 4-4 Table 4-2 Standard IR instructions 4-9 Table 4-3 Recommended implementation defined IR instructions for IEEE 1149. 1-compliance 4-10 Table 4-4 DPACC and APACc aCK responses 4-14 Table 4-5 JTAG-DP target response summary, when previous scan was a DPACC access .4-19 Table 4-6 JTAG-DP target response summary, when previous scan was an APACC access 4-20 Table 4-7 Summary of JTAG-DP host responses 4-21 Table 5-1 Target response summary for dP read transaction requests 5-16 Table 5-2 Target response summary for AP read transaction requests 5-17 Table 5-3 Target response summary for dP write transaction requests .5-17 Table 5-4 Target response summary for AP write transaction requests 5-18 Table 5-5 Summary of host(debugger) responses to the SW-DP acknowledge 5-19 Table 6-1 Summary of Debug Port registers 6-2 Table 6-2 JTAG- DP register map………… 6-3 Table 6-3 SW-DP register map 6-5 Table 6-4 AP abort Register bit assignments 6-6 ARM IHI O031A Copyright o 2006 ARM Limited. All rights reserved. Table 6-5 Identification Code Register bit assignments………… 6-9 Table 6-6 JEDEC JEP-106 manufacturer id code, with arm limited values 6-9 Table 6-7 Control/Status Register bit assignments 6-10 Table 6-8 Control of pushed operation comparisons by masKlane 6-14 Table 6-9 Transfer Mode. TRNMODE bit definitions 6-14 Table 6-10 Bit assignments for the AP Select Register, SELECT 6-16 Table 6-1 CTRLSEL field bit definitions .6-17 Table 6-12 Bit assignments for the Wire Control Register(SW- DP only)…….….6-19 Table 6-13 Turnaround tri-state period field, TURNROUND, bit definitions 6-19 Table 6-14 Wire operating mode, WIREmode, bit definitions 6-20 Table 8-1 Summary of AddrInc field values 8-9 Table 8-2 Size field values when the MEM-AP supports different access sizes . .........8-13 Table 8-3 Byte-laning of memory accesses from the DRW 8-14 Table 8-4 Use of dbgSwEnable bit, bit [31], to control a slave memory port .8-20 Table 8-5 Use of dbgSwEnable bit, bit [31], to control the DBGSWENABLE signal..8-20 Table 9-1 JTAG Access Port JTAG port signals 9-9 Table 9-2 Summary of jTAG Engine Byte Command Protocol 9-10 Table 9-3 TMS packet encodings 9-11 Table 9-4 TDI_ TDO first byte(opcode)format 9-13 Table 9-5 TDI_TDO second byte(length byte), packed format 9-16 Table 10-1 Summary of the common access port (ap) register 10-3 Table 10-2 AP ldentification Register, IDR, bit assignments 10-4 Table 10-3 ARM AP Identification types…… 10-5 Table 11-1 Summary of Memory Access Port(MEM-AP)registers ..11-2 Table 11-2 Access information for the mem-ap registers 11-3 Table 11-3 Bit assignments for the MEM-AP Control/Status Word Register, CSW....11-6 Table 11-4 Bit assignments for the Transfer Address Register, TAR 11-8 Table 11-5 Bit assignments for the data read/write register, DRW 111-8 Table 11-6 Mapping of Banked Data Registers onto memory addresses 11-9 Table 11-7 Bit assignments for the Banked Data Registers, BDo to BD3 11-9 Table 11-8 Bit assignments for the Configuration Register,CFG,…,………, 11-10 Table 1 1-9 Bit assignments for the Debug Base Address Register, BASE, 11-12 Tab|e11-10 Legacy Debug Base Address Register format when there are no Legacy Debug Base Address Register format when holding? debug entries 国面面面面面 11-14 Tab|e11-11 base address value 11-14 Table 12-1 Summary of JTAG Access Port (JTAG-AP) registers 12-2 Table 12-2 Bank and Offset values for accessing the JTAG-AP registers 12-3 Table 12-3 Bit assignments for the JTAG-AP Control/Status Word Register, CSW.......12-5 Table 12-4 Bit assignments for the jtAG-aP port select Register, PSeL 128 Table 12-5 Bit assignments for the JTAG-AP Port Status Register, PSTA 12-10 Table 13-1 Summary of Component and Peripheral ID Registers 13-2 Table 13-2 Summary of the Component Identification Registers 13-4 Table 13-3 Component Class values in the component ID 13-5 Table 13-4 Component IDo Register bit assignments........... 13-6 Table 13-5 Component ID1 Register bit assignments 13-7 Table 13-6 Component ID2 Register bit assignments 13-7 Copyright C 2006 ARM Limited. All rights reserved ARM IHI 0031A

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2012-05-28 上传 大小:1.67MB
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评论 下载该资源后可以进行评论 共14条

robber_yang 很好。正在调试。需要这个。是对得文档。
2020-02-15
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yuncmt 在调试DAP ,这个文档帮助很大
2018-05-22
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falw985 官方的,比较权威
2017-10-06
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cat_lover 不错,十分感谢
2017-08-23
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citydremer 不积跬步无以至千里
2017-03-20
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