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A. Multiplexed JTAG Interface
One approach to reducing the pin-count for the debug in-
terface is to multiplex the JTAG interface in the time domain.
The JTAG interface has three functional pins (TDI, TDO
and TMS) each of which carries a data value that can be valid
on every clock cycle.
Dividing the clock by three enables each of these data val-
ues can be presented in turn on a shared data pin, thereby
reducing the pin count from four pins to only two.
This scheme has several obvious disadvantages:
— it reduces the bandwidth by a factor of three, reducing
debug performance;
— does not allow daisy-chaining of devices, making debug
of multi-device systems very difficult;
— it requires turnaround of the data pin from host to target
drive in a single data cycle, limiting the maximum oper-
ating frequency and further impacting performance.
The scheme maintains compatibility with JTAG test, but
the increased tester time is probably prohibitive.
B. Re-visiting the JTAG Standard, IEEE 1149.7
The IEEE 1149.7 Draft Standard for Reduced-pin and
Enhanced-functionality Test Access Port and Boundary Scan
Architecture [2] extends the 1149.1 standard with support for:
— multiple power modes;
— system level bypass;
— star topology;
— two-pin operation.
IEEE 1149.7 describes six classes of compliance (Fig. 2).
These classes are hierarchical, meaning that a device wishing
to benefit from the T4 two-pin operation must also implement
all of T0-T3, even though the device is targeted at debug and
not test.
This paper only provides a brief overview of IEEE 1149.7;
for a more detailed introduction, see [3].
Star topology
A star topology (Fig. 3) supports true power and clock iso-
lation; the access port or ports can be isolated from the power
and clocks of the components being debugged, continuing to
function even when power is removed from the component.
It also provides higher performance than daisy-chain to-
pology, as there is no need for un-addressed components to
be in a “pass through” bypass state.
IEEE 1149.7 provides commands to select a component to
address in star topology.
Command protocol
IEEE 1149.7 operation is controlled by command se-
quences sent over the JTAG interface. Because of the need
for backwards compatibility with IEEE 1149.1, these se-
quences consist of:
— special paths through the JTAG TAP state machine that
are benign if sent to an IEEE 1149.1 implementation that
has just been reset;
— out-of-band messaging using clock as data and data as
clock: by holding the clock signal TCK HIGH and tog-
gling the TMS signal, control messages can be sent out
of band of the data stream.
Out-of-band messages are used in two-pin operation to
change data multiplexing mode. This effectively embeds the
clock in the data signal, which is problematic for standard
synthesis flows. They are also used to provide online and
offline state selection.
IEEE 1149.7 also supports online and offline state selection
using the unlikely data sequence approach described herein in
Selecting a device from dormant mode.
Data multiplexing
In two-pin operation, IEEE 1149.7 uses only the TCK and
TMS pins. In this mode of operation, the pins are named
TCKC and TMSC, respectively. TDI and TDO data can be
multiplexed onto TMSC in a manner similar to that described
herein in Multiplexed JTAG Interface.
Thus TMSC is a bidirectional data pin. To support this,
IEEE 1149.7 specifies that TMSC is not driven for the sec-
ond phase of each clock cycle, and must either be sampled on
the rising edge of TCKC, or held by bus keepers to be sam-
pled on the falling edge.
This phase is used for turnaround on the bidirectional pin.
This need to establish a stable signal level in a half a clock
cycle impacts the maximum operating frequency of the inter-
face. (Fig. 4.)
System-on-Chip
Host
controller
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p
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3
D
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1
Debug
component
2
Access
Port
Protocol
converter
Fig. 3: Debug star topology
1149.1 compatibility
1149.7 command protocol
system level bypass
four pin star topology
two pin with advanced scan protocols
T5
T4
T3
T1
T2
T0
data instrumentation
Enhanced
debug
capability
Extended JTAG
capability
Fig. 2: IEEE 1149.7 compliance classes
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