# TinyMIPS
Implementation of TinyMIPS processor for USTB computer composition principle course design.
## TinyMIPS's ISA
| OpCode | Description |
| ------- | ----------- |
| ADDU | N/A |
| ADDIU | N/A |
| SUBU | N/A |
| SLT | N/A |
| SLTU | N/A |
| AND | N/A |
| LUI | N/A |
| OR | N/A |
| XOR | N/A |
| SLL | N/A |
| SLLV | N/A |
| SRAV | N/A |
| SRLV | N/A |
| BEQ | N/A |
| BNE | N/A |
| JAL | N/A |
| JALR | N/A |
| LB | N/A |
| LBU | N/A |
| LW | N/A |
| SB | N/A |
| SW | N/A |
With no exceptions/interrupts supported.
## Recommended Implementation Order
1. Register file;
2. Basic pipeline and `ADDU` instruction;
3. `ADDIU` and `LUI` instruction;
4. Handle data dependencies;
5. Jump/Branch instructions;
6. Memory accessing instructions;
7. Handle data dependencies again (pipeline controller).
## Note
If you are using Vivado, after importing source files, you may need to do the following things:
1. Go to "Tools - Settings... - General - Verilog options", add `src\cpu\include` to search paths.
2. Select all include files in "Project Manager", then right click and click "Set Global Include".
cpu.zip（5级流水线结构的CPU实现）
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2020-05-25
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cpu.zip （58个子文件） 
cpu 
README.md 1KB mmu StaticMMU.v 1KB include opcode.v 970B sim.v 357B bus.v 865B funct.v 881B debug.v 188B pcdef.v 105B iobuf.v 1KB segpos.v 372B TinyMIPS.v 9KB ip InternalCrossbar InternalCrossbar.dcp 220KB simulation fifo_generator_vlog_beh.v 442KB hdl axi_infrastructure_v1_1_vl_rfs.v 29KB axi_crossbar_v2_1_vl_rfs.v 304KB axi_infrastructure_v1_1_0.vh 8KB fifo_generator_v13_2_vhsyn_rfs.vhd 2.34MB blk_mem_gen_v8_4_vhsyn_rfs.vhd 14.18MB axi_data_fifo_v2_1_vl_rfs.v 71KB fifo_generator_v13_2_rfs.v 582KB axi_register_slice_v2_1_vl_rfs.v 121KB generic_baseblocks_v2_1_vl_rfs.v 109KB fifo_generator_v13_2_rfs.vhd 1.38MB InternalCrossbar.veo 8KB InternalCrossbar.xci 330KB InternalCrossbar_sim_netlist.v 264KB synth InternalCrossbar.v 21KB InternalCrossbar_sim_netlist.vhdl 339KB InternalCrossbar_ooc.xdc 2KB InternalCrossbar_stub.vhdl 7KB InternalCrossbar.vho 9KB doc 
axi_crossbar_v2_1_changelog.txt 6KB sim InternalCrossbar.v 20KB InternalCrossbar_stub.v 6KB InternalCrossbar.xml 2.19MB sim RAM.v 1KB ROM.v 907B core pipeline PipelineController.v 720B PipelineDeliver.v 563B stage wb WB.v 2KB mem MEMWB.v 2KB MEM.v 4KB id ID.v 3KB BranchGen.v 3KB IDEX.v 3KB OperandGen.v 2KB RegGen.v 2KB FunctGen.v 796B MemGen.v 1KB if IFID.v 599B PC.v 1KB ex EXMEM.v 2KB EX.v 3KB Core.v 13KB storage RegFile.v 2KB RegReadProxy.v 2KB bus AXIAdapter.v 6KB mycpu_top.v 11KB资源评论
