0741-3106 (c) 2015 IEEE. Personal use is permitted, but republication/redistribution requires IEEE permission. See http://www.ieee.org/publications_standards/publications/rights/index.html for more information.
This article has been accepted for publication in a future issue of this journal, but has not been fully edited. Content may change prior to final publication. Citation information: DOI 10.1109/LED.2016.2525761, IEEE Electron
Device Letters
1
Abstract—Tunable threshold voltage of a thin-film transistor
(TFT) is highly desirable for designing multifunctional electronic
circuits. In this work, an ultrathin SnO
x
capping layer was
adopted to modify the threshold voltage of bottom-gate
amorphous indium-gallium-zinc-oxide (a-IGZO) TFTs. A
threshold voltage shift from 15.2 to -9.0 V was observed as the
SnO
x
thicknesses increased from 0 to 19 nm, accompanying by a
sizable increase of the intrinsic electron concentration in the
channel layer. It was believed that the SnO
x
capping layer can
extract loosely bound oxygen from the a-IGZO, which was
supported by the SnO
x
composition variation with its thickness.
Combining an uncovered a-IGZO TFT with a SnO
x
capped
a-IGZO TFT, an Enhancement/Depletion inverter with a voltage
gain up to 45.9 was successfully demonstrated.
Index Terms—Amorphous indium-gallium-zinc-oxide
(a-IGZO), Tin oxides (SnO
x
), thin-film transistor, inverter,
capping layer.
I. INTRODUCTION
morphous indium-gallium-zinc-oxide thin film transistor
(a-IGZO TFT) arrays have attracted ever-increasing
attention as backplanes in active matrix liquid crystal displays
(AMLCDs) or active-matrix organic light-emitting diode
displays (AMOLEDs) [1]. Meanwhile, there have been various
attempts to use a-IGZO TFTs in logic circuits [2],
photodetectors [3], memory devices [4], bio-sensors [5] and so
on. Oxide-based inverters, acting as “built blocks” of logic
circuits, are extensively studied in recent years.
Complementary inverters using p-type SnO
x
/n-type In
2
O
3
[6]
or hybrid n-type IGZO/p-type pentacene [7],
complementary-like inverters based on ambipolar SnO TFTs
[8], resistor-loaded inverters, and enhancement/depletion (E/D)
inverters have already been demonstrated. Among them, the
E/D inverter utilizing two n-channel TFTs with different
threshold voltage (V
th
) is a promising supplementary
technology for complementary logic circuits.
In order to tune the V
th
difference as much as possible,
various methods have been reported, such as varying the active
layer thickness [9], adopting distinct active layer material [10],
selectively inducing the negative bias illumination temperature
stress (NBITS) to the load TFT [11], and applying a constant
This work is supported by the National Natural Science Foundation of China
(Grant No. 61474126), and National Basic Research Program of China
(2012CB933003).
M. Wang, L. Y. Liang, H. Luo, S. N. Zhang, H. L. Zhang, K. Javaid and H.
T. Cao are with Ningbo Institute of Material Technology and Engineering,
Chinese Academy of Sciences, & Key Laboratory of Additive Manufacturing
Materials of Zhejiang Province, Ningbo 315201, People‟s Republic of China.
(E-mail: h_cao@nimte.ac.cn ; lly@nimte.ac.cn ).
K. Javaid is also with the Department of Physics, GC University
Faisalabad, Allama Iqbal Road, 38000 Faisalabad, Pakistan.
positive bias on the top gate [12], etc. However, these inverters
demonstrated either low voltage gains (< 40) or rather
complicated fabrication processes, limiting their applications.
Passivation layers with a thickness larger than 100 nm
were generally deposited to improve the electrical stability of
TFTs. However, various passivation layers (such as SiO
x
[13],
MgF
2
[14]) fabricated in vacuum system were found to not only
shift the V
th
negatively but also induce a very large off-current.
In this letter, by introducing a thin SnO
x
capping layer onto the
uncovered back channel surface (Bottom-gate top-contact TFT
structure), tunable V
th
of a-IGZO TFTs was achieved without
scarifying other device properties. Then an E/D inverter with a
voltage gain up to 45.9 was constructed by connecting an
uncovered a-IGZO TFT with a SnO
x
-covered one. This E/D
inverter has a relatively simple fabrication process, manifesting
a good application potential for the future logic circuits based
on oxide semiconductors.
II. DEVICE STRUCTURE AND FABRICATION
Bottom-gate transistors using a-IGZO as the channel layer
were fabricated at room temperature. A-IGZO thin films were
deposited on SiO
2
(100 nm)/Si substrate by RF sputtering,
applying a 2 in. IGZO target (1:1:1 mol. % of In
2
O
3
:Ga
2
O
3
:
ZnO) at a power of 80 W. The base pressure of the chamber was
less than 4 × 10
−4
Pa. 30 nm channel films were deposited in a
100% Ar atmosphere at a constant pressure of 0.21 pa (Ar flow
= 6 sccm). Afterwards, a shadow mask was used to define the
channel length and width of 400 and 800 μm, respectively.
Ti/Au (30 nm/30 nm) source/ drain electrodes were deposited
by electron beam evaporation using the second shadow mask.
The devices were then annealed at 250
o
C in the air for 1 hour.
Amorphous SnO
x
films with different thicknesses were
deposited at room temperature onto the back channel surface of
the fabricated a-IGZO TFTs through electron beam evaporation
(Deposition details were reported elsewhere [15]). Finally, an
E/D inverter was fabricated by connecting a bare TFT as the
driver and an 8.5 nm SnO
x
-covered TFT as the load. The
fabricated TFTs and inverters are finally passivated by SU-8
photo-resist to improve the device stability.
III. RESULTS AND DISCUSSION
Surface morphologies of the a-IGZO films covered with
or without amorphous SnO
x
films were investigated using
atomic force microscope (AFM), as seen in Figure 1. These
surfaces are apparently smooth without obvious embossment.
As shown in figure 1(d), the root mean square (RMS)
roughness as a function of the SnO
x
thickness is ranging from
0.50-0.60 nm, indicating that the deposition of the SnO
x
Mei Wang, Lingyan Liang, Hao Luo, Shengnan Zhang, Hongliang Zhang, Kashif Javaid, and
Hongtao Cao
Threshold voltage tuning in a-IGZO TFTs with ultrathin
SnO
x
capping layer and application to Depletion-Load
Inverter
Coupled Dual-Gate Oxide-based Transistors on
Sodium Alginate Electrolytes
A
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