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NCV7321 LIN 收发器,独立-综合文档
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NCV7321 LIN 收发器,独立
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© Semiconductor Components Industries, LLC, 2016
August, 2016 − Rev. 14
1 Publication Order Number:
NCV7321/D
NCV7321
Stand-alone LIN Transceiver
Description
The NCV7321 is a fully featured local interconnect network (LIN)
transceiver designed to interface between a LIN protocol controller
and the physical bus. The transceiver is implemented in I3T
technology enabling both high−voltage analog circuitry and digital
functionality to co−exist on the same chip.
The NCV7321 LIN device is a member of the in−vehicle
networking (IVN) transceiver family.
The LIN bus is designed to communicate low rate data from control
devices such as door locks, mirrors, car seats, and sunroofs at the
lowest possible cost. The bus is designed to eliminate as much wiring
as possible and is implemented using a single wire in each node. Each
node has a slave MCU−state machine that recognizes and translates
the instructions specific to that function. The main attraction of the
LIN bus is that all the functions are not time critical and usually relate
to passenger comfort.
Features
• LIN−Bus Transceiver
♦ LIN Compliant to Specification Revision 2.x (Backwards
Compatible to Version 1.3) and J2602
♦ Bus Voltage $45 V
♦ Transmission Rate 1 kbps to 20 kbps
♦ Supports K−Line Bus Architecture
• Protection
♦ Thermal Shutdown
♦ Indefinite Short−Circuit Protection on Pins LIN and WAKE
Towards Supply and Ground
♦ Load Dump Protection (45 V)
♦ Bus Pins Protected Against Transients in an Automotive
Environment
• EMI Compatibility
♦ Integrated Slope Control
• Modes
♦ Normal Mode: LIN Transceiver Enabled, Communication via the
LIN Bus is Possible, INH Switch is On
♦ Sleep Mode: LIN Transceiver Disabled, the Consumption from
V
BB
is Minimized, INH Switch is Off
♦ Standby Mode: Transition Mode reached either after Power−up or
after a Wake−up Event, INH Switch is on
♦ Wake−up Bringing the Component from Sleep Mode into Standby
Mode is Possible either by LIN Command or a Digital Signal on
WAKE Pin (e.g. External Switch)
Quality
• NCV Prefix for Automotive and Other Applications Requiring
Unique Site and Control Change Require− ments; AEC−Q100
Qualified and PPAP Capable
• These Devices are Pb−Free, Halogen Free/BFR Free and are RoHS
Compliant
www.onsemi.com
PIN CONNECTIONS
DFN8 (Top View)
See detailed ordering and shipping information in the package
dimensions section on page 12 of this data sheet.
ORDERING INFORMATION
1
8
MARKING
DIAGRAMS
SOIC−8:
x = Specific Device Code
0 = NCV7321D10
1 = NCV7321D11
2 = NCV7321D12
DFN8:
y = Specific Device Code
2 = NCV7321MW2
F = Fab Location Code
= (NCV7321D11R2G only)
A = Assembly Location
L = Wafer Lot
Y = Year
W = Work Week
G = Pb−Free Package
NV7321−x
FALYW
G
1
8
SOIC−8
CASE 751
1
DFN8
CASE 506DG
NV73
21−y
ALYWG
G
1
5
6
7
81
2
3
4
RxD
TxD
INH
EN
LIN
V
BB
GND
WAKE
SOIC−8 (Top View)
5
6
7
81
2
3
4
RxD
TxD
INH
EN
LIN
V
BB
GND
WAKE
(Note: Microdot may be in either location)
EP
![](https://csdnimg.cn/release/download_crawler_static/19016582/bg2.jpg)
NCV7321
www.onsemi.com
2
RECOMMENDED OPERATING RANGES AND KEY TECHNICAL CHARACTERISTICS
Table 1. RECOMMENDED OPERATING RANGES AND KEY TECHNICAL CHARACTERISTICS
Symbol Parameter Min Typ Max Unit
V
BB
Nominal Battery Operating Voltage (Note 1) 5 12 27
V
Load Dump Protection 45
I
BB
_SLP Supply Current in Sleep Mode 20
mA
V
LIN
LIN Bus Voltage −45 45 V
V
WAKE
Operating DC Voltage on WAKE Pin 0 V
BB
V
Maximum Rating Voltage on WAKE Pin −35 45 V
V
INH
Operating DC Voltage on INH Pin 0 V
BB
V
V_Dig_IO Operating DC Voltage on Digital IO Pins (EN, RxD, TxD) 0 5.5 V
T
JSD
Junction Thermal Shutdown Temperature 150 165 185 °C
T
amb
Operating Ambient Temperature −40 +125 °C
V
ESD
Electrostatic Discharge Voltage (all pins) Human Body Model (Note 2) −4 +4 kV
Version NCV7321D11/D12/MW2; no filter on LIN
Electrostatic Discharge Voltage (LIN) System Human Body Model (Note 3)
−10 +10 kV
V
TRAN
Version NCV7321D12/MW2;
Voltage transients (DCC method), pin LIN
According to SAE J2962−1, Class C (Note 4)
−85 +85 V
Functional operation above the stresses listed in the Recommended Operating Ranges is not implied. Extended exposure to stresses beyond
the Recommended Operating Ranges limits may affect device reliability.
1. Below 5 V on V
BB
in normal mode, the bus will either stay recessive or comply with the voltage level specifications and transition time
specifications as required by SAE J2602. It is ensured by the battery monitoring circuit. Above 27 V on V
BB
, LIN communication is operational
(LIN pin toggling) but parameters cannot be guaranteed. For higher battery voltage operation above 27 V, LIN pull−up resistor must be
selected large enough to avoid clamping of LIN pin by voltage drop over external pull−up resistor and LIN pin min current limitation.
2. Equivalent to discharging a 100 pF capacitor through a 1.5 kW resistor conform to MIL STD 883 method 3015.7.
3. Equivalent to discharging a 150 pF capacitor through a 330 W resistor. System HBM levels are verified by an external test−house.
4. Direct Capacitor Coupling (DCC) method according to SAE J2962−1 specification, referring to ISO 7637−3 Slow Transient Pulse. Coupling
Capacitor 10 nF. Tested with no external protections. Verified by an external test house.
Table 2. THERMAL CHARACTERISTICS
Parameter Symbol Value Unit
Thermal characteristics, SOIC−8 (Note 5)
Thermal Resistance Junction−to−Air, Free air, 1S0P PCB (Note 6)
Thermal Resistance Junction−to−Air, Free air, 2S2P PCB (Note 7)
R
q
JA
R
q
JA
125
75
°C/W
°C/W
Thermal characteristics, DFN8 (Note 5)
Thermal Resistance Junction−to−Air, Free air, 1S0P PCB (Note 6)
Thermal Resistance Junction−to−Air, Free air, 2S2P PCB (Note 7)
R
q
JA
R
q
JA
140
47
°C/W
°C/W
5. Refer to ELECTRICAL CHARACTERISTICS, RECOMMENDED OPERATING RANGES and/or APPLICATION INFORMATION for Safe
Operating parameters.
6. Values based on test board according to EIA/JEDEC Standard JESD51−3, signal layer with 10% trace coverage.
7. Values based on test board according to EIA/JEDEC Standard JESD51−7, signal layers with 10% trace coverage.
![](https://csdnimg.cn/release/download_crawler_static/19016582/bg3.jpg)
NCV7321
www.onsemi.com
3
BLOCK DIAGRAM
LIN
NCV7321
GND
RxD
INH
Thermal
shutdown
TxD
COMP
Slope Control
Filter
EN
POR
State
&
Wake−up
Control
WAKE
time−out
Osc
Figure 1. Block Diagram
+
−
V
BB
V
BB
TYPICAL APPLICATION
NCV7321
GND
8
3
6
1
2
4
5
7
INH
LIN
WAKE
RxD
TxD
EN
Microcontroller
GND
VCC
bat
3.3/5V
VBAT
LIN
WAKE
GND
KL30
LIN−
BUS
KL31
ECU
Figure 2. Typical Application Diagram for a Master Node
V
BB
Table 3. PIN DESCRIPTION
Pin Name Description
1 RxD Receive Data Output; Low in Dominant State; Open−Drain Output
2 EN Enable Input, Transceiver in Normal Operation Mode when High, Pull−down Resistor to GND
3 WAKE High Voltage Digital Input Pin to Apply Local Wake−up, Sensitive to Falling Edge, Pull−up Current Source to V
BB
4 TxD Transmit Data Input, Low for Dominant State, Pull−down to GND (Switchable Strength for Wake−up Source Recognition)
5 GND Ground
6 LIN LIN Bus Output/Input
7 V
BB
Battery Supply Input
8 INH Inhibit Output, Switch Between INH and V
BB
can be Used to Control External Regulator or Pull−up Resistor on LIN Bus
− EP Exposed Pad. Recommended to connect to GND or left floating in application (DFN8 package only).
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