Volume 3 ：Chapter 23. 计时器1
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Cyclone V 器件手册
卷 3：硬核处理器系统技术参考手册
2012 年 11 月
反馈 订阅
ISO
9001:2008
Registered
23. 计时器
硬核处理器系统 (HPS) 提供 4 个、32-bit 的与 level 4 (L4) 外设总线相连接的通用计
时器。当 32-bit 二进制倒计时计时器达到零时，计时器有选择性地生成一个中断。计
时器是 Synopsys
®
DesignWare
®
APB 计时器 (DW_apb_timers) 外设的实例。
1 微处理器单元 (MPU) 子系统提供额外的计时器。要了解关于 MPU 中计时器的更多信息，
请参考
Cyclone V 器件手册
第3卷的
Cortex
-
A9 MPU System
章节。
计时器的功能
■ 支持中断生成
■ 支持自由运行模式
■ 支持用户定义的计数模式
计时器结构图和系统集成
图 23–1 显示了计时器的结构图。每个计时器包括用于控制和状态寄存器 (CSR) 访问
的从接口、寄存器模块和达到零时生成中断的可编程 32
-
bit 递减计数器。计时器在时
钟管理器驱动的单一时钟域上进行操作。
图 23–1. 计时器结构图
Timer
MPU
Register Block
Interrupt and
System Reset Control
Interrupt
Reset
Manager
Clock
Manager
L4 Peripheral Bus
(osc1_clk)
Slave Interface
November 2012
cv_54023-1.2
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