iv Altera Corporation
Stratix GX Device Handbook, Volume 1
Contents
Chapter 4. Stratix GX Architecture
Logic Array Blocks ................................................................................................................................ 4–1
LAB Interconnects ............................................................................................................................ 4–1
LAB Control Signals ......................................................................................................................... 4–2
Logic Elements ....................................................................................................................................... 4–3
LUT Chain & Register Chain .......................................................................................................... 4–5
addnsub Signal ................................................................................................................................. 4–5
LE Operating Modes ........................................................................................................................ 4–5
Clear & Preset Logic Control ........................................................................................................ 4–10
MultiTrack Interconnect ..................................................................................................................... 4–11
TriMatrix Memory ............................................................................................................................... 4–18
Memory Modes ............................................................................................................................... 4–19
Parity Bit Support ........................................................................................................................... 4–21
Shift Register Support .................................................................................................................... 4–21
Memory Block Size ......................................................................................................................... 4–22
Independent Clock Mode .............................................................................................................. 4–40
Input/Output Clock Mode ........................................................................................................... 4–42
Read/Write Clock Mode ............................................................................................................... 4–44
Single-Port Mode ............................................................................................................................ 4–45
Digital Signal Processing Block ......................................................................................................... 4–46
Multiplier Block .............................................................................................................................. 4–52
Adder/Output Blocks ................................................................................................................... 4–56
Modes of Operation ....................................................................................................................... 4–59
DSP Block Interface ........................................................................................................................ 4–65
PLLs & Clock Networks ..................................................................................................................... 4–68
Global & Hierarchical Clocking ................................................................................................... 4–68
Enhanced & Fast PLLs ................................................................................................................... 4–76
Enhanced PLLs ............................................................................................................................... 4–82
Fast PLLs .......................................................................................................................................... 4–93
I/O Structure ........................................................................................................................................ 4–96
Double-Data Rate I/O Pins ......................................................................................................... 4–103
External RAM Interfacing ........................................................................................................... 4–107
Programmable Drive Strength ................................................................................................... 4–110
Open-Drain Output ...................................................................................................................... 4–111
Slew-Rate Control ........................................................................................................................ 4–112
Bus Hold ........................................................................................................................................ 4–112
Programmable Pull-Up Resistor ................................................................................................ 4–113
Advanced I/O Standard Support .............................................................................................. 4–113
Differential On-Chip Termination ............................................................................................. 4–118
MultiVolt I/O Interface ............................................................................................................... 4–120
Power Sequencing & Hot Socketing ............................................................................................... 4–121
IEEE Std. 1149.1 (JTAG) Boundary-Scan Support ........................................................................ 4–122
Chapter 5. Configuration & Testing
SignalTap Embedded Logic Analyzer ................................................................................................ 5–1
Configuration ......................................................................................................................................... 5–1
Operating Modes .............................................................................................................................. 5–1
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