4 Intel Confidential 610272
3.2.2 eSPI Slave Configuration Register Data (SLV_CFG_REG_DATA)—Offset 4004h .
104
3.2.3 Peripheral Channel Error for Slave 0 (PCERR_SLV0)—Offset 4020h ............ 105
3.2.4 Peripheral Channel Error for Slave 1 (PCERR_SLV1)—Offset 4024h ............ 107
3.2.5 Virtual Wire Channel Error for Slave 0 (VWERR_SLV0)—Offset 4030h.........108
3.2.6 Virtual Wire Channel Error for Slave 1 (VWERR_SLV1)—Offset 4034h.........110
3.2.7 Flash Access Channel Error for Slave 0 (FCERR_SLV0)—Offset 4040h......... 111
3.2.8 Link Error for Slave 0 (LNKERR_SLV0)—Offset 4050h ..............................113
3.2.9 Link Error for Slave 1 (LNKERR_SLV1)—Offset 4054h ..............................115
4 P2SB Bridge (D31:F1) ............................................................................................116
4.1 P2SB PCI Configuration Registers Summary ........................................................ 116
4.1.1 PCI Identifier (PCIID)—Offset 0h........................................................... 117
4.1.2 PCI Command (PCICMD)—Offset 4h ...................................................... 117
4.1.3 Revision ID (PCIRID)—Offset 8h ........................................................... 118
4.1.4 Class Code (PCICC)—Offset 9h .............................................................119
4.1.5 PCI Header Type (PCIHTYPE)—Offset Eh ................................................ 119
4.1.6 Sideband Register Access BAR (SBREG_BAR)—Offset 10h ........................ 120
4.1.7 Sideband Register BAR High DWORD (SBREG_BARH)—Offset 14h ............. 120
4.1.8 PCI Subsystem Identifiers (PCIHSS)—Offset 2Ch..................................... 121
4.1.9 VLW Bus:Device:Function (VBDF)—Offset 50h ........................................ 121
4.1.10 ERROR Bus:Device:Function (EBDF)—Offset 52h ..................................... 122
4.1.11 Routing Configuration (RCFG)—Offset 54h.............................................. 122
4.1.12 High Performance Event Timer Configuration (HPTC)—Offset 60h .............. 123
4.1.13 IOxAPIC Configuration (IOAC)—Offset 64h .............................................124
4.1.14 IOxAPIC Bus:Device:Function (IBDF)—Offset 6Ch ................................... 125
4.1.15 HPET Bus:Device:Function (HBDF)—Offset 70h ....................................... 125
4.1.16 Display Bus:Device:Function (DISPBDF)—Offset C0h ............................... 126
4.1.17 ICC Register Offsets (ICCOS)—Offset C4h .............................................. 127
4.1.18 SBI Address (SBIADDR)—Offset D0h ..................................................... 127
4.1.19 SBI Data (SBIDATA)—Offset D4h .......................................................... 128
4.1.20 SBI Status (SBISTAT)—Offset D8h ........................................................ 128
4.1.21 SBI Routing Identification (SBIRID)—Offset DAh ..................................... 129
4.1.22 SBI Extended Address (SBIEXTADDR)—Offset DCh..................................130
4.1.23 P2SB Control (P2SBC)—Offset E0h ........................................................ 130
4.1.24 Power Control Enable (PCE)—Offset E4h ................................................ 131
4.1.25 Sideband Register Posted 0 (SBREGPOSTED0)—Offset 200h ..................... 132
4.1.26 Sideband Register Posted 1 (SBREGPOSTED1)—Offset 204h ..................... 133
4.1.27 Sideband Register Posted 2 (SBREGPOSTED2)—Offset 208h ..................... 133
4.1.28 Sideband Register Posted 3 (SBREGPOSTED3)—Offset 20Ch..................... 133
4.1.29 Sideband Register Posted 4 (SBREGPOSTED4)—Offset 210h ..................... 134
4.1.30 Sideband Register Posted 5 (SBREGPOSTED5)—Offset 214h ..................... 134
4.1.31 Sideband Register Posted 6 (SBREGPOSTED6)—Offset 218h ..................... 135
4.1.32 Sideband Register Posted 7 (SBREGPOSTED7)—Offset 21Ch..................... 135
4.1.33 Endpoint Mask 0 (EPMASK0)—Offset 220h.............................................. 136
4.1.34 Endpoint Mask 1 (EPMASK1)—Offset 224h.............................................. 136
4.1.35 Endpoint Mask 2 (EPMASK2)—Offset 228h.............................................. 137
4.1.36 Endpoint Mask 3 (EPMASK3)—Offset 22Ch .............................................137
4.1.37 Endpoint Mask 4 (EPMASK4)—Offset 230h.............................................. 137
4.1.38 Endpoint Mask 5 (EPMASK5)—Offset 234h.............................................. 138
4.1.39 Endpoint Mask 6 (EPMASK6)—Offset 238h.............................................. 138
4.1.40 Endpoint Mask 7 (EPMASK7)—Offset 23Ch .............................................139
5 PMC Controller (D31:F2) ........................................................................................140
5.1 Power Management Configuration Registers Summary ..........................................140
5.1.1 Device Vendor ID (DEVVENDID)—Offset 0h ............................................ 140
