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1300 Henley Court

Pullman, WA 99163

509.334.6306

www.digilentinc.com

NetFPGA-1G-CML™ Board Reference Manual

Revised July 16, 2014

This manual applies to the NetFPGA-1G-CML rev. F

DOC#: 6015-502-001

Other product and company names mentioned may be trademarks of their respective owners.

Page 1 of 21

Overview

The NetFPGA-1G-CML is a versatile, low-cost network hardware development platform featuring a Xilinx® Kintex®-

7 XC7K325T FPGA and includes four Ethernet interfaces capable of negotiating up to 1 GB/s connections. 512 MB

of 800 MHz DDR3 can support high-throughput packet buffering while 4.5 MB of QDRII+ can maintain low-latency

access to high demand data, like routing tables. Rapid boot configuration is supported by a 128 MB BPI Flash,

which is also available for non-volatile storage applications. The standard PCIe form factor supports high speed x4

Gen 2 interfacing. The FMC carrier connector provides a convenient expansion interface for extending card

functionality via Select I/O and GTX serial interfaces. The FMC connector can support SATA-II data rates for

network storage applications. The FMC connector can also be used to extend functionality via a wide variety of

other cards designed for communication, measurement, and control.

The NetFPGA-1G-CML is designed to support the Stanford NetFPGA architecture with reference designs available

through the NetFPGA GitHub Organization (www.github.com/organizations/NetFPGA). It is fully compatible with

Xilinx Vivado™ and ISE® Design Suites as well as Xilinx SDK for embedded software design.

The NetFPGA-1G-CML board.

 Xilinx Kintex-7 XC7K325T-1FFG676 FPGA

 Low-jitter 200 MHz oscillator

 Four 10/100/1000 Ethernet PHYs with

RGMII

 X4 Gen 2 PCI Express

 X16 4.5 MB QDRII+ static RAM (450 MHz)

 X8 512 MB DDR3 dynamic RAM (800 MHz)

 1-Gbit BPI Flash

 SD card slot

 32-bit PIC microcontroller

 USB microcontroller

 Real time clock

 Crypto-authentication chip

 High pin count FMC connector (VITA 57)

withh 100 Select-IO and 4 GTX serial pairs

 Two Pmod connectors

 Four on-board LEDs and four on-board

general-purpose buttons

NetFPGA-1G-CML™ Board Reference Manual

Other product and company names mentioned may be trademarks of their respective owners.

Page 2 of 21

The Kintex-7 XC7K325T-1FFG676 FPGA has ample

logic and I/O capacity for supporting a wide range

of designs with the following capabilities:

 50,950 slices, each containing four 6-

input LUTs and eight flip-flops

 Over 16 Mbit of fast on-chip block RAM

 Ten clock management tiles with one PLL

and one mixed-mode clock manager each

 840 DSP slices

 Integrated PCI Express

 Integrated AES bitstream encryption and

SHA-256 authentication with battery-

backed encryption key

 400 Select I/O ports (250 high range, 150

high speed)

 Eight 6.6 Gb/s GTX serial transceivers

1 FPGA Configuration

The system logic configuration is stored within the FPGA in SRAM-based memory cells. This data defines the

FPGA's logic functions and circuit connections, but it is volatile since it remains valid only as long as power is

applied. Because of this, the device is configured (i.e., programmed) every time it is turned-on. In addition, it may

also be re-configured at any time power is applied. Once power is removed, the most recently programmed logic

configuration is lost. The configuration data is commonly called a bitstream which is most often contained in files

of type ".bit" or ".mcs". These files may be created several different ways using Xilinx development software.

The FPGA may be configured from three different sources. These include the on-board BPI flash, an off-board USB

flash drive, or via a PC. The NetFPGA-1G follows a specific configuration sequence when it powers up and comes

out of reset. If a valid "download.bit" file is detected on an attached UBS flash drive, that bitstream will be used to

program the FPGA. The flash drive must be FAT formatted, contain a single "download.bit" file, and be attached to

the USB-HOST port (J13) with jumper JP4 in place. If no flash drive bitstream is detected, an attempt will be made

to configure the device from the on-board BPI flash address 0x0. If no flash bitstream is available, the board idles

until it is programmed from a PC. PC programming can be done either via a USB cable connected to the USB PROG

port (J12), or a JTAG programming cable connected to the Xilinx PROG CABLE port (J15). Any flash drive bitstreams

that are not built for the Xilinx XC7K325T FPGA will be ignored. This power-on programming sequence can be re-

initiated at any time after power is applied by depressing the red PROG button (BTN5).

Both Digilent and Xilinx distribute free software that can be used to transfer bitstreams from a PC as well as create

bitstream files to load via a flash drive. Digilent's Adept and Xilinx's iMPACT applications can directly program the

FPGA using a .bit file a standard USB A to Micro B cable connected to J12 or through any of several Digilent JTAG

programming cables connected to J15. The on-board BPI flash is programmed via similar means. When

NetFPGA-1G-CML™ Board Reference Manual

Other product and company names mentioned may be trademarks of their respective owners.

Page 3 of 21

programming the BPI, iMPACT transfers a .mcs format bitstream to the flash in a two-step process. iMPACT first

programs the FPGA directly with a special purpose BPI flash interface. It will then transfer the .mcs bitstream to the

flash through that interface. This process is fully automated by the iMPACT program, so a designer only needs to

be concerned with the creation of the .mcs file using Xilinx's design software.

More details on configuring the XC7K325T FPGA via the on-board BPI (using Master BPI mode), via the PIC USB-

HOST (using Slave Serialmode), and via the JTAG mode can be found in the Xilinx 7 Series FPGAs Configuration User

Guide (UG470).

2 Power Supplies

The NetFPGA-1G requires a 12V, 5A, or greater power source. Power is supplied via the J17 Molex connector at the

rear of the PCB, as is often done with high performance PC graphics cards. No power is supplied via the PCIe

motherboard bus connector.

The NetFPGA-1G can be powered using the 6-pin PCIe power supply connector (Fig. 1) of any standard ATX power

supply. When installed on a PC motherboard, you can directly plug the 6-pin PCIe power supply connector of your

PC power supply into J17. When used standalone (without a motherboard), you need to short pins 15 and 16

(pulling down PS_ON signal) of the main 20-pin connector of the standard ATX power supply to power-on the ATX

unit (Fig.1).

Figure1. Left: NetFPGA-1G can be powered by plugging the 6-pin PCIe power connector in J17; Right: Pin 16 and 17 are shorted using a jumper

to power on a standard ATX power supply when used standalone.

Analog Devices voltage regulators provide a number of on-board power and reference voltages that are derived

from the main 12V supply, as shown in Table 1. Supply power-on and power-off sequencing follows manufacturer

recommendations. The on-board battery that supports encryption key storage and the real-time clock is charged

when the PCB is powered on and should not need to be replaced during the lifetime of the board.

VADJ controls the signal levels used between the FMC connector and two FPGA Select I/O banks and can be set to

1.2 V, 1.8 V, 2.5 V, or 3.3 V as needed. The board is shipped with the VADJ supply turned off. To turn on VADJ,

jumper JP5 is installed and the FPGA is configured to drive the VADJ_EN pin (AD16) high. The VADJ voltage is

selected via the FPGA configuration using pins AF19 and AF20 as shown in Table 1.

When jumper JP4 is in place, the USB HID connector provides 5V at up to 0.5 A to external USB devices, including

keyboards, mice, and thumb drives. An Analog Devices ADM1177 hot swap controller and power monitor is used

to allow safe device attachment and removal while the board is powered up. The PIC can also measure USB

current and voltage by accessing the on-chip power monitor via the PIC I2C peripheral bus.

NetFPGA-1G-CML™ Board Reference Manual

Other product and company names mentioned may be trademarks of their respective owners.

Page 4 of 21

The Xilinx Kintex-7 Data Sheet: DC and AC Switching Characteristics (DS182) provides more information on the

power supply requirements of the FPGA board.

Supply

Derived From

Application

5.0 V

12.0 V

USB HID; FMC

3.3 V

12.0 V

SD Card; Ethernet PHYs; Cypress FX2LP; Microchip PIC; BPI

Flash; FPGA I/O Banks 14,15; FMC; PMODs

2.0 V

5.0 V

FPGA auxiliary supply, VCCBAT; Backup battery; Real-time clock

backup.

1.8 V

12.0 V

QDRII+ supply

1.8 V

3.3 V

FPGA GTX transceiver Quad PLL

1.5 V

12.0 V

DDR3; FPGA I/O Bank 34

1.2 V

12.0 V

FPGA GTX transceiver termination

1.0 V

12.0 V

FPGA GTX analog supply

1.0 V

3.3 V

FPGA Core

0.9 V

3.3 V

QDRII+ reference

0.75 V

3.3 V

DDR3 reference

VADJ

12.0 V

FPGA I/O Banks 12, 13; FMC; Configurable.

SET_VADJ2

FPGA AF20

SET_VADJ1

FPGA AF19

VADJ

1.2 V

1.8 V

2.5 V

3.3 V

Table 1. On-board power supplies.

3 Oscillators and Clocks

On-board oscillators support various board subsystems. A low-jitter 125 MHz oscillator is provided for the Ethernet

PHYs and a 50 MHz oscillator drives the FPGA master configuration clock. The Cypress FX2LF and Microchip PIC

microcontroller each contain on-chip oscillators running at 24 MHz and 8 MHz, respectively.

The main FPGA system clock is provided by an ultra-low-jitter 200 MHz differential oscillator connected to pins

AA2 and AA3 in I/O bank 34. This can drive up to ten internal PLLs (Phase Locked Loops) and MMCMs (Mixed-

Mode Clock Managers) on the FPGA for high-performance multi-clock-domain designs. Please refer to the Xilinx 7-

Series Clock Resources User Guide (UG472) for more details on FPGA internal clocking resources.

4 FPGA Memory

The XC7K325T FPGA includes 445 on-chip Block RAMs (BRAMs) of 36Kb, or 4096 bytes with two-bit error

correction, which amounts to a total of 1.78 MB of on-chip, error-corrected static RAM that can be used for a

variety of purposes ranging from program storage for deeply embedded "bare metal" applications to data

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