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FEATURES DESCRIPTION

APPLICATIONS

FUNCTIONAL DIAGRAM

EYE PATTERN

1.5 Gbps

-1 PRBS

750 MHz

= 3.3 V, T

= 25°C, V

 = 200 mV, V

= 1.2 V, V

= 3.3 V, R

= 50 Ω

Vertical Scale = 500 mV/div

Horizontal Scale = 200 ps/div

SN65CML100

SLLS547 – NOVEMBER 2002

1.5-Gbps LVDS/LVPECL/CML-TO-CML TRANSLATOR/REPEATER

• Provides Level Translation From LVDS or

This high-speed translator/repeater is designed for

LVPECL to CML, Repeating From CML to CML

signaling rates up to 1.5 Gbps to support various

high-speed network routing applications. The driver

• Signaling Rates

(1)

up to 1.5 Gbps

output is compatible with current-mode logic (CML)

• CML Compatible Output Directly Drives

levels, and directly drives 50- Ω or 25- Ω loads

Devices With 3.3-V, 2.5-V, or 1.8-V Supplies

connected to 1.8-V, 2.5-V, or 3.3-V nominal supplies.

• Total Jitter < 70 ps

The capability for direct connection to the loads may

eliminate the need for coupling capacitors. The

• Low 100 ps (Max) Part-To-Part Skew

receiver input is compatible with LVDS (TIA/EIA-644),

• Wide Common-Mode Receiver Capability

LVPECL, and CML signaling levels. The receiver

Allows Direct Coupling of Input Signals

tolerates a wide common-mode voltage range, and

• 25 mV of Receiver Input Threshold Hysteresis

may also be directly coupled to the signal source.

Over 0-V to 4-V Common-Mode Range

The internal data path from input to output is fully

differential for low noise generation and low

• Propagation Delay Times, 800 ps Maximum

pulse-width distortion.

• 3.3-V Supply Operation

The V

pin is an internally generated voltage supply

• Available in SOIC and MSOP Packages

to allow operation with a single-ended LVPECL input.

For single-ended LVPECL input operation, the

unused differential input is connected to V

as a

• Level Translation

switching reference voltage. When used, decouple

• 622-MHz Central Office Clock Distribution

with a 0.01- µ F capacitor and limit the current

sourcing or sinking to 400 µ A. When not used, V

BB• High-Speed Network Routing

should be left open.

• Wireless Basestations

This device is characterized for operation from –40 ° C

• Low Jitter Clock Repeater

(1)

to 85 ° C.

(1) The signaling rate of a line is the number of voltage

transitions that are made per second expressed in the units

bps (bits per second).

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas

Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

PRODUCTION DATA information is current as of publication date.

Products conform to specifications per the terms of the Texas

Instruments standard warranty. Production processing does not

necessarily include testing of all parameters.

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ABSOLUTE MAXIMUM RATINGS

RECOMMENDED OPERATING CONDITIONS

PACKAGE DISSIPATION RATINGS

SN65CML100

SLLS547 – NOVEMBER 2002

These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam

during storage or handling to prevent electrostatic damage to the MOS gates.

ORDERING INFORMATION

PART NUMBER PART MARKING PACKAGE STATUS

SN65CML100D CML100 SOIC Production

SN65CML100DGK NWB MSOP Production

over operating free-air temperature range unless otherwise noted

(1)

UNIT

Supply voltage range

(2)

–0.5 V to 4 V

Sink/source ± 0.5 mA

Voltage range, (A, B, Y, Z) 0 V to 4.3 V

A, B, Y, Z, and GND ± 5 kV

Human Body Model

(3)

Electrostatic

All pins ± 2 kV

discharge

Charged-Device Model

(4)

All pins ± 1500 V

Continuous power dissipation See Dissipation Rating Table

stg

Storage temperature range –65 ° C to 150 ° C

Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds 260 ° C

(1) Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings

only, and functional operation of the device at these or any other conditions beyond those indicated under recommended operating

conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

(2) All voltage values, except differential I/O bus voltages, are with respect to network ground terminal.

(3) Tested in accordance with JEDEC Standard 22, Test Method A114-A.7.

(4) Tested in accordance with JEDEC Standard 22, Test Method C101.

MIN NOM MAX UNIT

Supply voltage 3 3.3 3.6 V

3.3-V nominal supply at terminator 3 3.3 3.6

Terminator supply voltage 2.5-V nominal supply at terminator 2.375 2.5 2.625

1.8-V nominal supply at terminator 1.7 1.9 V

| Magnitude of differential input voltage 0.1 1 V

Input voltage (any combination of common-mode or input signals) 0 4 V

Output current 400 µ A

Operating free-air temperature –40 85 ° C

≤ 25 ° C DERATING FACTOR

(1)

= 85 ° C

PACKAGE

POWER RATING ABOVE T

= 25 ° C POWER RATING

DGK 425 mW 3.4 mW/ ° C 221 mW

D 725 mW 5.8 mW/ ° C 377 mW

(1) This is the inverse of the junction-to-ambient thermal resistance when board-mounted and with no air flow.

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DEVICE CHARACTERISTICS

INPUT ELECTRICAL CHARACTERISTICS

OUTPUT ELECTRICAL CHARACTERISTICS

SN65CML100

SLLS547 – NOVEMBER 2002

PARAMETER MIN NOM MAX UNIT

Supply current, device only 9 12 mA

Switching reference voltage

(1)

1890 1950 2010 mV

(1) V

parameter varies 1:1 with V

over recommended operating conditions (unless otherwise noted)

PARAMETER TEST CONDITIONS MIN TYP

(1)

MAX UNIT

Positive-going differential input voltage

IT+

100

threshold

See Figure 1 and Table 1 mV

Negative-going differential input voltage

IT-

–100

threshold

ID(HYS)

Differential input voltage hysteresis,V

IT+

– V

IT–

25 mV

= 0 V or 2.4 V, Second input at 1.2 V –20 20

Input current (A or B inputs) µ A

= 4 V, Second input at 1.2 V 33

= 1.5 V, V

= 0 V or 2.4 V,

–20 20

Second input at 1.2 V

I(OFF)

Power off input current (A or B inputs) µ A

= 1.5 V, V

= 4 V, Second input at 1.2 V 33

Input offset current (|I

- I

|) V

= V

IB,

0 ≤ V

≤ 4 V –6 6 µ A

= 0.4 sin (4E6 π t) + 0.5 V 3

Differential input capacitance pF

= 0 V 3

(1) All typical values are at 25 ° C and with a 3.3-V supply.

over recommended operating conditions (unless otherwise noted)

PARAMETER TEST CONDITIONS MIN TYP

(1)

MAX UNIT

Output high voltage

(2)

–60 V

–10 V

= 50 Ω , V

= 3 V to 3.6 V or V

= 2.5 V ±5%,

Output low voltage

(2)

–1100 V

–800 V

–640 mV

See Figure 2

| Differential output voltage magnitude 640 780 1000 mV

Output high voltage

(3)

–60 V

–10 V

= 25 Ω , V

= 3 V to 3.6 V or V

= 2.5 V ±5%,

Output low voltage

(3)

–550 V

–400 V

–320 mV

See Figure 2

| Differential output voltage magnitude 320 390 500 mV

Output high voltage

(2)

–170 V

–10 V

Output low voltage

(2)

= 50 Ω , V

= 1.8 V ±5%, See Figure 2 V

–1100 V

–800 V

–640 mV

| Differential output voltage magnitude 570 780 1000 mV

Output high voltage

(3)

–85 V

–10 V

Output low voltage

(3)

= 25 Ω , V

= 1.8 V ±5%, See Figure 2 V

–500 V

–400 V

–320 mV

| Differential output voltage magnitude 285 390 500 mV

= 0.4 sin (4E6 π t) + 0.5 V 3

Differential output capacitance pF

= 0 V 3

(1) All typical values are at 25 ° C and with a 3.3-V supply.

(2) Outputs are terminated through 50- Ω resistors to V

, CML level specifications are referenced to V

and tracks 1:1 with variation of

(3) Outputs are terminated through 25- Ω resistors to V

; CML level specifications are referenced to V

and tracks 1:1 with variation of

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