An Overview on Writing
a
VHDL
Testbench
Dan Biederman
Member
of
Technical Staff
Hughes Missile Systems Company
Bldg
805,
M/S
F6
P.
0.
Box
11337
Tucson,
AZ
85734
Abstract
This paper is an overview of VHDL
testbenches and other related topics. It has been
written for a digital design engineer with little
VHDL or programming experience to get a
better understanding of writing VHDL, and
using a testbench. The future of VHDL is also
discussed.
Introduction
Finding errors in the design of
electrical circuits before the fabrication or
production stage can reduce the product
development time and cost. One way that
engineers have to do this is by building a device
around the prototype circuit called a hardware
testbench. A hardware testbench would
generate the inputs (Stimulus) and review the
outputs (Monitor) of the device.
In recent years the design of digital
circuitry, such as Application Specific
Integrated Circuits (ASICs) and Programmable
Logic Devices (PLDs), has been done using a
software programming language known as a
Hardware Description Language oL) such as
VHDL.
One of the reasons for this is that
VHDL
can ideally be synthesized into any current gate-
level technology such as an ASIC or PLD.
Thus an ASIC designed today can be redesigned
several years later reusing the software code that
was written originally.
Once a digital device has been
designed, it needs to be tested. One method of.
testing these devices and their
surroundmg
circuitry is to use a HDL testbench before the
fabrication of the device.
This paper discusses
the methodologies of HDL testbenches and
reviews their uses in the design process at the
gate level, board level, and system levels to
verlfy the proper operation of a digital design.
Writing a
VHDL
testbench
A testbench has three major parts, the
stimulus, the monitor, and the device under test
@UT)
as shown in Figure la. The stimulus is
the part of the testbench that controls the input
signal values. Thls portion of the software
program should contain
all
of the information
that the DUT needs to perform its job properly.
This may include address and data buses,
interrupt signals, enables, etc.
The monitor,
on
the other hand, checks
or verifies the outputs of the
DUT.
This is
usually done by waiting for the simulation event,
and then checking that the event occurred with
an “Assert” statement. By venfylng the DUT
using “Assert” statements, one can usually save
simulation time, because
all
signal traces need
not be stored, and also save engmeering time,
because
all
of the signals need not be verified
individually.
In using VHDL, one can have the
monitor and the stimulus in the same program
(entity) as shown in Figure lb. If a digital
designer wishes to use only one program, and
still
keep
the
stimulus
separate
from
the
monitor, it can be acheved by using different
processes for the monitor and different process
for the stimulus.
384
0-8186-7873-9/97 $10.00
0
1997
IEEE
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