STM32 UART DMA方式接收发送代码

/** ****************************************************************************** * @file stm32mp157fxx_ca7.h * @author MCD Application Team * @brief CMSIS stm32mp157fxx_ca7 Device Peripheral Access Layer Header File. * * This file contains: * - Data structures and the address mapping for all peripherals * - Peripheral's registers declarations and bits definition * - Macros to access peripherals registers hardware * ****************************************************************************** * @attention * * <h2><center>&copy; Copyright (c) 2019 STMicroelectronics. * All rights reserved.</center></h2> * * This software component is licensed by ST under BSD 3-Clause license, * the "License"; You may not use this file except in compliance with the * License. You may obtain a copy of the License at: * opensource.org/licenses/BSD-3-Clause * ****************************************************************************** */ /** @addtogroup CMSIS_Device * @{ */ /** @addtogroup stm32mp157fxx_ca7 * @{ */ #ifndef __STM32MP157Fxx_CA7_H #define __STM32MP157Fxx_CA7_H #ifdef __cplusplus extern "C" { #endif /* __cplusplus */ /** * @brief Bit position definition inside a 32 bits registers */ #define B(x) \ ((uint32_t) 1 << x) /** * @} */ /** @addtogroup Peripheral_interrupt_number_definition * @{ */ /** * @brief STM32MP1XX Interrupt Number Definition, according to the selected device * in @ref Library_configuration_section */ typedef enum IRQn { /****** Cortex-A Processor Specific Interrupt Numbers ***************************************************************/ /* Software Generated Interrupts */ SGI0_IRQn = 0, /*!< Software Generated Interrupt 0 */ SGI1_IRQn = 1, /*!< Software Generated Interrupt 1 */ SGI2_IRQn = 2, /*!< Software Generated Interrupt 2 */ SGI3_IRQn = 3, /*!< Software Generated Interrupt 3 */ SGI4_IRQn = 4, /*!< Software Generated Interrupt 4 */ SGI5_IRQn = 5, /*!< Software Generated Interrupt 5 */ SGI6_IRQn = 6, /*!< Software Generated Interrupt 6 */ SGI7_IRQn = 7, /*!< Software Generated Interrupt 7 */ SGI8_IRQn = 8, /*!< Software Generated Interrupt 8 */ SGI9_IRQn = 9, /*!< Software Generated Interrupt 9 */ SGI10_IRQn = 10, /*!< Software Generated Interrupt 10 */ SGI11_IRQn = 11, /*!< Software Generated Interrupt 11 */ SGI12_IRQn = 12, /*!< Software Generated Interrupt 12 */ SGI13_IRQn = 13, /*!< Software Generated Interrupt 13 */ SGI14_IRQn = 14, /*!< Software Generated Interrupt 14 */ SGI15_IRQn = 15, /*!< Software Generated Interrupt 15 */ /* Private Peripheral Interrupts */ VirtualMaintenanceInterrupt_IRQn = 25, /*!< Virtual Maintenance Interrupt */ HypervisorTimer_IRQn = 26, /*!< Hypervisor Timer Interrupt */ VirtualTimer_IRQn = 27, /*!< Virtual Timer Interrupt */ Legacy_nFIQ_IRQn = 28, /*!< Legacy nFIQ Interrupt */ SecurePhysicalTimer_IRQn = 29, /*!< Secure Physical Timer Interrupt */ NonSecurePhysicalTimer_IRQn = 30, /*!< Non-Secure Physical Timer Interrupt */ Legacy_nIRQ_IRQn = 31, /*!< Legacy nIRQ Interrupt */ /****** STM32 specific Interrupt Numbers ****************************************************************************/ WWDG1_IRQn = 32, /*!< Window WatchDog Interrupt */ PVD_AVD_IRQn = 33, /*!< PVD & AVD detector through EXTI */ TAMP_IRQn = 34, /*!< Tamper interrupts through the EXTI line */ RTC_WKUP_ALARM_IRQn = 35, /*!< RTC Wakeup and Alarm (A & B) interrupt through the EXTI line */ TZC_IT_IRQn = 36, /*!< TrustZone DDR address space controller */ RCC_IRQn = 37, /*!< RCC global Interrupt */ EXTI0_IRQn = 38, /*!< EXTI Line0 Interrupt */ EXTI1_IRQn = 39, /*!< EXTI Line1 Interrupt */ EXTI2_IRQn = 40, /*!< EXTI Line2 Interrupt */ EXTI3_IRQn = 41, /*!< EXTI Line3 Interrupt */ EXTI4_IRQn = 42, /*!< EXTI Line4 Interrupt */ DMA1_Stream0_IRQn = 43, /*!< DMA1 Stream 0 global Interrupt */ DMA1_Stream1_IRQn = 44, /*!< DMA1 Stream 1 global Interrupt */ DMA1_Stream2_IRQn = 45, /*!< DMA1 Stream 2 global Interrupt */ DMA1_Stream3_IRQn = 46, /*!< DMA1 Stream 3 global Interrupt */ DMA1_Stream4_IRQn = 47, /*!< DMA1 Stream 4 global Interrupt */ DMA1_Stream5_IRQn = 48, /*!< DMA1 Stream 5 global Interrupt */ DMA1_Stream6_IRQn = 49, /*!< DMA1 Stream 6 global Interrupt */ ADC1_IRQn = 50, /*!< ADC1 global Interrupts */ FDCAN1_IT0_IRQn = 51, /*!< FDCAN1 Interrupt line 0 */ FDCAN2_IT0_IRQn = 52, /*!< FDCAN2 Interrupt line 0 */ FDCAN1_IT1_IRQn = 53, /*!< FDCAN1 Interrupt line 1 */ FDCAN2_IT1_IRQn = 54, /*!< FDCAN2 Interrupt line 1 */ EXTI5_IRQn = 55, /*!< External Line[9:5] Interrupts */ TIM1_BRK_IRQn = 56, /*!< TIM1 Break interrupt