+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Legal Partition Candidates ;
+-----------+-------+----------------+--------------+----------------+--------+-----------------+---------------+-----------------+-------+----------------+--------------+------------------+-------------------+
; Hierarchy ; Input ; Constant Input ; Unused Input ; Floating Input ; Output ; Constant Output ; Unused Output ; Floating Output ; Bidir ; Constant Bidir ; Unused Bidir ; Input only Bidir ; Output only Bidir ;
+-----------+-------+----------------+--------------+----------------+--------+-----------------+---------------+-----------------+-------+----------------+--------------+------------------+-------------------+
; comb_3 ; 7 ; 0 ; 0 ; 0 ; 1 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ;
+-----------+-------+----------------+--------------+----------------+--------+-----------------+---------------+-----------------+-------+----------------+--------------+------------------+-------------------+
实验目的： 1.构建基于verilog语言的组合逻辑电路和时序逻辑电路； 2.掌握verilog语言的电路设计技巧 3.完成如
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实验目的：
1.构建基于verilog语言的组合逻辑电路和时序逻辑电路；
2.掌握verilog语言的电路设计技巧
3.完成如 （113个子文件） 
logic_design.vpr.ammdb 332B logic_design.root_partition.cmp.ammdb 287B logic_design.map.ammdb 138B logic_design.v.bak 2KB logic_design.cmp.bpm 781B logic_design.map.bpm 757B logic_design.cmp.cdb 5KB logic_design.root_partition.cmp.cdb 3KB logic_design.map.cdb 3KB logic_design.root_partition.map.cdb 2KB logic_design.sgdiff.cdb 2KB logic_design.rtlv_sg.cdb 2KB logic_design.map_bb.cdb 2KB logic_design.(2).cnf.cdb 2KB logic_design.(1).cnf.cdb 2KB logic_design.root_partition.map.hbdb.cdb 1KB logic_design.(0).cnf.cdb 1KB logic_design.(4).cnf.cdb 1KB logic_design.(3).cnf.cdb 882B logic_design.rtlv_sg_swap.cdb 518B logic_design.root_partition.map.reg_db.cdb 218B logic_design.cdf 372B logic_util_heursitic.dat 2KB logic_design.db_info 155B logic_design.db_info 155B logic_design.tiscmp.slow_1200mv_n40c.ddb 113KB logic_design.tiscmp.slow_1200mv_125c.ddb 112KB logic_design.tiscmp.fast_1200mv_n40c.ddb 112KB logic_design.asm_labs.ddb 27KB logic_design.tis_db_list.ddb 255B logic_design.pti_db_list.ddb 192B logic_design.root_partition.cmp.dfp 33B logic_design.done 26B logic_design.root_partition.map.dpi 868B logic_design.root_partition.map.hbdb.hb_info 46B logic_design.cmp.hdb 11KB logic_design.root_partition.cmp.hdb 11KB logic_design.sgdiff.hdb 11KB logic_design.pre_map.hdb 11KB logic_design.map.hdb 10KB logic_design.rtlv.hdb 10KB logic_design.root_partition.map.hbdb.hdb 10KB logic_design.root_partition.map.hdb 10KB logic_design.map_bb.hdb 10KB logic_design.(0).cnf.hdb 1KB logic_design.(1).cnf.hdb 841B logic_design.(2).cnf.hdb 778B logic_design.(4).cnf.hdb 663B logic_design.(3).cnf.hdb 639B logic_design.hier_info 620B logic_design.hif 637B logic_design.stingray_io_sim_cache.99um_tt_1200mv_0c_slow.hsd 1.18MB logic_design.stingray_io_sim_cache.99um_tt_1200mv_85c_slow.hsd 1.18MB logic_design.stingray_io_sim_cache.99um_ff_1200mv_0c_fast.hsd 1.17MB logic_design.cycloneive_io_sim_cache.31um_ii_1200mv_n40c_slow.hsd 733KB logic_design.cycloneive_io_sim_cache.31um_ff_1200mv_n40c_fast.hsd 732KB logic_design.cycloneive_io_sim_cache.31um_ii_1200mv_125c_slow.hsd 732KB
logic_design.lpc.html 573B logic_design.cmp.idb 2KB logic_design.ipinfo 178B logic_design.jdi 231B logic_design.root_partition.map.kpt 227B logic_design.cmp_merge.kpt 226B logic_design.map.kpt 224B logic_design.cmp.kpt 222B logic_design.root_partition.cmp.kpt 218B logic_design.cmp.logdb 14KB logic_design.root_partition.cmp.logdb 4B logic_design.map.logdb 4B logic_design.map_bb.logdb 4B logic_design.pin 40KB prev_cmp_logic_design.qmsg 54KB logic_design.fit.qmsg 22KB logic_design.map.qmsg 15KB logic_design.sta.qmsg 11KB logic_design.asm.qmsg 2KB logic_design.qpf 1KB logic_design.qsf 4KB logic_design.qws 3KB logic_design.root_partition.cmp.rcfdb 2KB logic_design.cmp.rdb 20KB logic_design.routing.rdb 8KB logic_design.sta.rdb 7KB logic_design.asm.rdb 1KB logic_design.map.rdb 1KB logic_design.lpc.rdb 454B logic_design.pplq.rdb 247B README 653B logic_design.fit.rpt 151KB logic_design.sta.rpt 59KB logic_design.map.rpt 23KB logic_design.flow.rpt 8KB logic_design.asm.rpt 7KB logic_design.sld_design_entry_dsc.sci 217B logic_design.sld_design_entry.sci 217B logic_design.root_partition.map.hbdb.sig 32B logic_design.fit.smsg 703B logic_design.sof 1.12MB logic_design.fit.summary 625B logic_design.map.summary 479B共 113 条
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