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s3c2450 user manual
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2009-09-16
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s3c2450 user manual,simple summary
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Product Technical Brief
S3C2450
May 2008
This document contains specification and information
on a product developed or under development.
Samsung Electronics reserves the right to change
specification or information without any prior notice.
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SAMSUNG's S3C2450 is a 32/16-bit RISC
cost-effective, low power, high performance
micro-processor solution for general
applications including the GPS Navigation and
Mobile Phone markets. Additionally, in order to
allow for lower system costs, higher
performance and low power, the S3C2450 is
fabricated using the 65nm low power CMOS
process.
The S3C2450 carries revolutionary upgrades
with respect to the S3C2443. Most notably,
upgrade to ARM926EJ core, 2D Graphics
Accelerator, added low power mode, as well
as embedded internal ROM/RAM for secure
boot and moviNAND booting and low power
audio decoding. Furthermore, peripheral and
feature upgrades have also been made to
increase performance, as well as flexibility.
Examples include upgraded Camera I/F, USB
Device 2.0 HS, MMC/HS-MMC/SD/SDHC
ports, HS-SPI ports and upgraded memory
interfaces.
All in all, the S3C2450 presents a low-cost,
highly embedded solution with upgraded
features
Overview Features Summary
ARM926EJ CPU 400/533MHz with 16KB I-cache and
16KB D-cache
Dual port external memory controller: DRAM/ROM
control and chip select logic
64KB internal general purpose SRAM
32KB internal ROM for moviNAND booting
LCD controller with DMA-dedicated: 24bpp, 2-PIP
Camera controller with BT 601/656 input: 8MP Input
and 2MP scaled TFT-LCD, 4K color STN, and 180°
rotator
2D graphics accelerator
8-ch DMAs with external request pins
4-ch UART (3Mbps) with IrDA 1.0 (64B FIFO)
2-ch HS-SPI (50Mbps)
CF+ & ATA I/F
2-ch IIC: multi-master
2-ch IIS: PCM and AC97 I/F
2-ch SD host controller version 2.0 (SDHC) &
Multimedia card protocol version 2.11 (HS-MMC)
1 port USB Host v1.1 full speed
1 port USB Device v2.0 high speed
4-ch PWM timers & 1-ch internal timers
Real time clock & Watch dog timer
2 PLLs with on-chip clock generator
Power modes: Normal, Idle, Stop & Deep Stop, Sleep
and Power-off
10-ch 12-bit ADC (Touch screen interface)
65nm low-power technology and MtCMOS technology
incorporated
Package
400-pins FBGA (0.5mm Pitch), 13 x 13 x 1.4mm
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