JZ4760B Mobile Application Processor User-Interfaces Programming Manual
n 君正 IngeniO 1 LCD Controller a日:aa:a:日a:a:日a:aa:aa 1.1 Overview 1.2 Pin Description 1.3 Block Diagram 1.4 LCD Display Timing 1.5 TV Encoder tim 1.6 OSD Graphic 1.6.1 co| or Key…… 1.7 TV Graphic 2 1.7.1 Different Display Field 12 1.8 Register description 14 1.8.1 Configure Register(LCDCFG) 1,, 15 1.8.2 Control Register(LCDCTRL 18 1.8.3 Status Register(LCDSTATE) 19 1.8.4○ SD Configure Register( LCDOSDO)……,… .20 1.8.5 OSD Control Register(LCDOSDCTRL) 20 1.8.6 OSD State Register(LCDOSDS) 1.8.7 Background Color Register(LCDBGC) 1.8.8 Foreground Color Key Register O(LCDKEYO) 1.8.9 Foreground Color Key Register 1(LCDKEY1) 23 1.8. 10 ALPHA Register (LCDALPHA 1.8.11 IPU Restart(LCDIPUR) 1.8.12 RGB Control (LCDRGBC) I..... 24 1.8.13 Virtual Area Setting(LCDVAT) 26 1.8. 14 Display Area Horizontal Start/End Point ( LCDDaH) 26 1.8.15 Display Area Vertical Start/End Point( LCDDAV)……… …27 1.8. 16 Foreground O XY Position Register (LCDXYPO) 27 1.8. 17 Foreground 0 PART2 XY Position Register (LCDXYPO_ PART2) 27 1.8.18 Foreground 1 XY Position Register (LCDXYP1) 28 1.8. 19 Foreground o Size Register (LCDSIZEO 28 1.8.20 Foreground0PART2 Size Register(LCDs|zE0_PART2)……………………29 1.8.21 Foreground 1 Size Register (LCDSIZE1) 1.8.22 Vertical Synchronize Register(LCDVSYNC) 1.8.23 Horizontal Synchronize Register(LCDHSYNC) 30 1.8.24 PS Signal Setting(LCDPS) 30 1.8.25 CLS Signal Setting( LCDCLS).…… 1.8.26 SPL Signal Setting(LCDSPL 1.8.27 REV Signal Setting(LCDREV) .31 1.828 nterrupt ID Register(LCD|D).…… 2 1.8.29 Descriptor Address Registers(LCDDAX, LCDDAO PART2)..... .32 君正 1.8.30 Source Address Registers(LCDSAX, LCDSAO PART2) 33 1.8. 31 Frame ID Registers(LCDF IDX, LCDFIDO PART2) 1.8.32 DMA Command Registers(LCDCMDX, LCDCMDO_ PART2) 34 1.8.33 DMA OFFSIZE Registers(LCDOFFSX,0 PART2) 1.8.34 DMA Page Width Registers(LCDPWX, 0 PART2) 1.835 DMA Commend Counter Registers( LCDCNUMX)……… 666 1.8.36 Foreground X Size in Descriptor(LCDDESSIZEX, LCDDESSIZEO_ PART2) 1.8. 37 Priority level threshold configure Register (LCDPCFG) 37 1.9 LCD Controller Pin Mapping 39 1.9.1 TFT and CCIR Pin Mapping 1.9.2 Single Panel STN Pin Mapping 41 1.9.3 Dual Panel STN Pin Mapping 42 1.9.4 Data mapping to gpo function 1.10 Display Timing 4 1.10.1 General 16-bit and 18-bit TFT Timing 44 1.10.28- bit Serial TFT Timing…… 1.10.3 Special TFT Timing 4 1.10.4 Delta RGB panel timing 47 1.10.5 RGB Dummy mode timing 48 1.11 Format of palette 1.11.1STN 1.11.2TFT 49 1.12 Format of frame Buffer 50 1.12.116bpp… 1.12218bpp…… 1.12324bpp. 1.12. 4 16bpp with alpha 50 1.12.5 18bpp with alpha 50 1.12.6 24bpp with alpha.. 51 1.12.7 24bpp compressed 51 1.13 Format of Data Pin Utilization 52 1.13. 1 Mono stN 52 1.13.2 Color StN ∴52 1.13, 3 18-bit ParalleI TFt 52 1.13. 16-bit Parallel tft 52 1.13.5 8-bit Serial TFT(24bpp) .53 1.14 LCD Controller Operation .54 1.141 Set lCD Controller ahb clock and pixel clock 54 1.14.2 Enabling the Controller 1 .54 1.14.3 Disabling the Controller 1.144 Resetting the Controller..…,… 55 1.145 Frame buffer palette Buffer 1.14.6Cc|R601CC|R656 55 n 君正 IngeniO 1.14.7 OSD Operation 55 1.14.8 Descriptor Operation 1.149 Pu direct connect mode 1.14.10 VGA output 9996 1.14.11 Foreground o divide mode 2 Smart LCD Controller 63 2.1 Overview 63 2.2 Structure 2.3 Pin Description 2. 4 Register Description 65 2.4.1 SLCD Configure Register(MCFG) 2.4.2 SLCD Control Register(MCTRL) 67 2.4.3 SLCD Status Register(MSTATE) 67 2.4.4 SLCD Data Register(MDATA) 68 2.5 System Memory Format 69 2.5.1 Data format 2.5.2 Command format 69 2.6 Transfer mode 70 2.6.1 DMA Transfer mode 70 2.6.2 Register Transfer Mode 1国 72 Timing...-- 2.7.1 Parallel Timing .::::: 73 2.7.2 Serial Timing 73 2.8 Operation Guide 74 2.8.1 DMA Operation 2.8.2 Register Operation 74 3 Decompressor ■■重日重日量D量量量11量量量量■ 76 3.1 Overview 76 3.2 Compress Method 76 3.3 Operation Guide 78 34 Limitations∴ 79 4T∨ Encoder 80 4.1 Overview 80 4.2 Structure 4.3 Pin Description 4.4 Register Description ∴83 4.4.1 TV Encoder Control Register (TVECR) 83 4.4.2 Frame configure register( FRCFG)…… 4.4.3 Signal level configure register 1, 2 and 3(SLCFG1, SLCFG2, SLCFG3 .86 4.4.4 Line timing configure register 1 and 2(LTCFG1, LTCFG2) 87 君正 4.4.5 Chrominance configure registers(CFREQ, CPHASE, CFCFG) 88 4.5 Switch between LCD panel and TV set 4.6 DAc 91 4.6.1 DAC Connection .91 4.6.2 DAC DC Character 91 4.6.3 DAC Power Down Setup Time 92 5 EPd Controller .93 5.1 Overview 93 5.2 EPDC Pin Mappings……… 94 5.3 Function Block Diagram 5.4 EPD Controller Registers 97 5.5 Registers Description ∴99 5.5.1 EPDC Control Registers 99 5.5.2 EPDC Status Register 5.5.3 EPDC ISR Register 100 5.5.4 EPDC Configuration register o 101 5.5.5 EPDC Configuration Register 1 ..102 5.5.6 EPDC Pipeline frame Register O .103 5.5.7 EPDC Pipeline frame register 1 104 5.5.8 EPDC Virtual Display Area Setting Register 104 5.5. 9 EPDC Vertical Display Area Setting Register .104 5.5.10 EPDC Horizontal Display Area Setting Register .105 5.5.11 EPDC Vertical Synchronous Start Pulse Setting 105 5.5. 12 EPDC Horizontal Synchronous Start Pulse setting 105 5.5.13 EPDC Gate Driver Clock Setting Register. 106 5514 EPDC Gate Output Enable Setting Register……… 106 5.5.15 EPDC Gate Driver Start Pulse setting…… 106 5.5.16 EPDC Source Driver Output Enable Setting Register 107 5.5. 17 EPDC Source Driver Start Pulse Setting Register ….107 5.5.18 EPDC Power Management Registers O 107 5.5. 19 EPDC Power Management Registers 1 .108 5.5.20 EPDC Power Management Registers 2 108 5.5.21 EPDC Power Management Registers 3 108 5.5.22 EPDC Power Management Registers 4 5.5.23 EPDC VCOM Registers 0-5 ∴109 5.5. 24 EPDC Border Voltage Setting Registers 110 5.5.25 EPDC Handwriting Mode Setting 110 5.5.26 EPDC Pipeline0-7 Position Registers 111 5.5.27 EPDC Pipeline 0-7 Size registers 5.6 Application Guide ..................... ∴.112 5.6.1 Pixel format in buffers 112 5.6.2 Waveform luT Format 112 n 君正 IngeniO 5.6.3 Power On/Off Sequence 113 5.6.4 Display Timing Setting 114 5.6.5 Update image/text flow 116 5.6.6 Multi-zone concurrent updating 117 5.6.7 Update VCOMO-5… 117 5.6.8 Handwriting mode 117 5.6.9 Border Display… 117 6 mage Process Unit… 18 6.1 Overview 118 6.1.1 Feature∴ .118 6.2 Block 119 6.3 Data flow 120 6.3.1 nput data...,,,… 6.3.2 Output data 120 6.3.3 Resize coefficients lut 120 6. 4 Registers Descriptions 12 6.4.1| PU Control Register…… .122 64.2| PU Status Register...,…… 124 6.4.3 PU address control register 125 6.4.4 Data Format Register 1“11面面 1国 4125 6.4.5 Input Y Data Address Register 127 6.4.6 Input U Data Address Register 127 6. 4.7 Input V Data Address Register 128 6.4.8 Input source tLB base address 128 6. 4.9 Destination tlb base address 129 6.4.10 tLB monitor 129 6.4.11 lB controller 129 6.4.12 Input Y Data Address of next frame Register ∴130 6.4.13 Input U Data Address of next frame Register 130 6.4.14 Input V Data Address of next frame Register 131 6.4.15 Source tlb base address of next frame ∴131 6. 4.16 Destination tlb base address of next frame 131 6.4.17 ADDRESS Mapping 132 6.4.18 Input Geometric Size Register 132 6.4.19 Input Y Data Line Stride Register 133 6.4.20 Input UV Data Line Stride Register 6.4.21 Output Frame Start Address Register 133 6. 4.22 Output Data Address of next frame Register 134 6.4.23 Output Geometric Size Register 134 6.4.24 Output Data Line Stride Register ∴135 64.25 CSC CO Coefficient Register .135 6.4.26 CSC C1 Coefficient Register 136 君正 6.427cscC2 Coefficient Register…… 6.4.28 CSC C3 Coefficient Register 137 6.4.29 CSC C4 Coefficient Register 137 6. 4.30 Resize Coefficients Table Index Register 138 6.4.31 Horizontal Resize Coefficients Look Up Table Register group.. 138 6. 4.32 Vertical Resize Coefficients Look Up Table Register group 143 6.4.33 Calculation for Resized width and height 144 6.4.34 CSC Offset Parameter Register 145 6.4.35 Picture enhance table 145 6.5 IPU Operation Flow 6.5.1 ata out to frame buffer 6.5.2 Data out to lcdc 148 6.5.3 Operation example ∴49 6.6 Special Instruction 152 Al Resizing size feature 152 \2 Color convention feature 152 A3 YUV/YCbCr to RGB CSC Equations ..152 A4 Output data package format(RGB order) 153 A5. Input data package format (RGB order)......... 154 A6. Source Data storing format in external memory (separated YUV Frame) 154 7 Alpha osd 155 7.1 Overview 155 7.2 Structure 7.3 Alpha blending functio ..157 7.4 Register Description ● 7. 4.1 Reg addr -Reg addr, Reg waddr 159 7.4.2 Reg addrlen ..160 7. 4.3 Slv reg_alphavalue.. 160 74.4 CTRL 161 7.4.5|NT ..162 7.5 Alpha osd operation 163 8 Camera Interface Module 164 8.1 Overview 164 8.1.1 Features 164 8.1.2 Pin Description .164 8.2 CIM Special Register 165 8.2.1 CIM Configuration Register(CIMCFG) 165 8.2.2 CIM Control Register(CIMCR) 168 8.23c| M Control Register2(C|MCR2)……… 画画 8.2.4 CIM Status Register(CIMST) 171 8.2.5 CIM Interrupt ID Register(CIMIID) 173 n 君正 IngeniO 826 CIM Descriptor Address(cMDA)…………… ∴.173 8.2.7 CIM Frame buffer Address Register(CIMFA) 174 8.2.8 CIM Frame ID Register(CIMFID) 174 8.2.9 CIM DMA Command Register(CIMCMD) 175 82.10 CIM Window- mage Size(CMS|ZE).…… 176 8.2.11 CIM Image Offset(CIMOFFSET) 176 8.2.12 CIMY Frame buffer Address Register (CIMYFA 177 8213 CIM Y DMA Command Register( CIMYCMD)…… 177 8.2.14 CIM Cb Frame buffer Address Register(CIMCBFA) 178 8.2.15 CIM Cb DMA Command Register (CIMCBCMD) 178 8216C| M Cr Frame buffer Address Register(C| MCRFA).……… 179 8.2.17 CIM DMA Cr Command Register(CIMCRCMD) 179 8.3 CIM Data Sampling Modes 180 8.3.1 Gated clock mode 4180 8.3.2 TU656 Interlace mode 180 8.3.3 TU656 Progressive Mode. 182 DMA Descriptors 183 8.4.1 4-Word Descriptor 183 8.4.2 8-Word Descriptor 183 8.5 Interrupt Generation 184 8.6 Software Operation .B ∴185 8.6.1 Enable cim with dma ..185 8. 6.2 Enable ciM without dMa 185 8.6.3 Disable cIM 185 9 nternal codec Interface 186 9. 1 Overview 186 9.1.1 Features 186 9.1.2 Signal D 9.1.3 Block Diagra 188 9.2 Mapped register descriptions 189 9.2.1 CODEC internal register access control(RGADW) 190 9.2.2 CODEC internal register data output(RGDATA) 191 9.3 Operation 192 9.3. 1 Access to internal registers of the embedded codec 192 9.3.2 CODEC controlling and typical operations 192 9.3.3 Power saving…………… 194 9.3.4 Pop noise and the reduction of it 194 94 Timing parameters.,……,… ..196 9.5 AC dc parameters 197 9.6 CODEC internal Registers 199 9.6.1 CODEC internal registers 199 9.7 Programmable gains.... 217 君正 9.8 Configuration of the headphone output stage 21 9. 9 Out-of-band noise filtering.. 222 9.10 Output short-circuit protection(headphone output) 223 9.11 Sampling frequency: FREQ 224 9.12 Programmable data word length 225 9.13 Ramping system note 226 9.14 AGC system guide 227 9. 14.1 AGc operating mode 227 9.15 Digital Mixer description 230 9.16 CODEC Operating modes 231 9.16.1 Power-On mode and Power-off mode 232 9.16.2 RESET mode 232 9.16. 3 STANDBY mode 232 9.16.4 SLEEP mode 232 9.16.5 Soft mute mode 233 9. 16.6 Power-Down mode and active mode 234 9.16.7 Working modes summary 235 9.17 SYs CLK turn-off and turn-on 9.18 Requirements on outputs and inputs selection and power-down modes.........237 9.19 Anti-pop operation sequences 238 9.19.1 Initialization and configuration 238 9. 19.2 Start up sequence(DAC) 23 9. 19.3 Shutdown sequence(DAC) .241 9. 19.4 Start up sequence(Line input) 242 9. 19.5 Shutdown sequence(Line input) 243 9.20 Circuits design suggestions 244 9.20. 1 Avoid quiet ground common currents 244 9.20.2 Headphone connection(Capacitor-coupled) 245 9.20.3 Microphone connection 245 9. 20.4 Description of the connections to the jack 248 9.20.5 PCB considerations 249 9.21 Analog characteristics 251 9.21. 1 Line input to audio adc path 251 9. 21.2 Microphone input to audio Adc path 251 9.21.3 Audio dac to headphone output path 252 9. 21.4 Audio dac to mono line output path ∴252 9. 21.5 Line input to headphone output path(analog bypass) 253 9.21.6 Microphone input to headphone output path(analog sidetone 253 9.21.7 Micbias and reference 254 10 AC97/2S/SPDIF Controller 255 10.1 Overview 10.1.1 Block Diagram