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Clock Gating Methodology
for
Power and CTS QoR
2
Agenda
•Objective
• Introduction to clock gating
• Clock gating methodology
– Overview
– RTL synthesis
– Physical synthesis
– Clock tree synthesis
– Summary of recommendations
• Sample results
• Planned enhancements
• Summary
3
Objective
• Describe the clock gating methodology to meet target
– Skew
– Insertion delay
–Power
• Discuss recommendations during
– RTL synthesis using Design Compiler
– Physical synthesis using IC Compiler or Physical Compiler
– Clock tree synthesis using IC Compiler or Astro
4
Agenda
•Objective
• Introduction to clock gating
• Clock gating methodology
– Overview
– RTL synthesis
– Physical synthesis
– Clock tree synthesis
– Summary of recommendations
• Sample results
• Planned enhancements
• Summary
5
What is Clock Gating?
• Register banks disabled during some clock cycles
– Typical implementation uses multiplexers
– Clock gating cell replaces multiplexers
EN
CLK
D
Q
gclk
Low
activity
EN
Q
D
CLK
High
activity
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