How To Successfully Use Gated Clocking in an ASIC design
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2010-01-20
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How To Successfully Use Gated Clocking
in an
ASIC Design
Darren Jones
MIPS Technologies, Inc.
dj@mips.com
ABSTRACT
Gated clocking is a true silver bullet for hardware designers. Using this technique, engineers can
improve all three major performance metrics of a circuit: speed, area, and power. Unfortunately,
EDA tools have traditionally lacked support for gated clocks. These limitations have relegated
clock gating to the full-custom design community. However, new features in synthesis and static
timing analysis tools have brought gated clocking to mainstream ASIC designers.
This paper discusses the pitfalls that still exist to using gated clocks in an ASIC design.
Furthermore, it suggests methodologies and workarounds that can be used to avoid these
problems so that gated clocking can be used successfully. The paper explains how gated clocking
impacts the following areas: logic synthesis, static timing analysis (STA), automatic test-pattern
generation (ATPG), clock tree synthesis, and standard-cell library design.
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