################################################################################
# Vivado (TM) v2017.2 (64-bit)
#
# README.txt: Please read the sections below to understand the steps required
# to simulate the design for a simulator, the directory structure
# and the generated exported files.
#
################################################################################
1. Simulate Design
To simulate design, cd to the simulator directory and execute the script.
For example:-
% cd questa
% ./top.sh
The export simulation flow requires the Xilinx pre-compiled simulation library
components for the target simulator. These components are referred using the
'-lib_map_path' switch. If this switch is specified, then the export simulation
will automatically set this library path in the generated script and update,
copy the simulator setup file(s) in the exported directory.
If '-lib_map_path' is not specified, then the pre-compiled simulation library
information will not be included in the exported scripts and that may cause
simulation errors when running this script. Alternatively, you can provide the
library information using this switch while executing the generated script.
For example:-
% ./top.sh -lib_map_path /design/questa/clibs
Please refer to the generated script header 'Prerequisite' section for more details.
2. Directory Structure
By default, if the -directory switch is not specified, export_simulation will
create the following directory structure:-
<current_working_directory>/export_sim/<simulator>
For example, if the current working directory is /tmp/test, export_simulation
will create the following directory path:-
/tmp/test/export_sim/questa
If -directory switch is specified, export_simulation will create a simulator
sub-directory under the specified directory path.
For example, 'export_simulation -directory /tmp/test/my_test_area/func_sim'
command will create the following directory:-
/tmp/test/my_test_area/func_sim/questa
By default, if -simulator is not specified, export_simulation will create a
simulator sub-directory for each simulator and export the files for each simulator
in this sub-directory respectively.
IMPORTANT: Please note that the simulation library path must be specified manually
in the generated script for the respective simulator. Please refer to the generated
script header 'Prerequisite' section for more details.
3. Exported script and files
Export simulation will create the driver shell script, setup files and copy the
design sources in the output directory path.
By default, when the -script_name switch is not specified, export_simulation will
create the following script name:-
<simulation_top>.sh (Unix)
When exporting the files for an IP using the -of_objects switch, export_simulation
will create the following script name:-
<ip-name>.sh (Unix)
Export simulation will create the setup files for the target simulator specified
with the -simulator switch.
For example, if the target simulator is "ies", export_simulation will create the
'cds.lib', 'hdl.var' and design library diectories and mappings in the 'cds.lib'
file.
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AXI4总线读写ram,内附仿真图
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AXI4总线读写ram,内附仿真图 (175个子文件)
xsim.ini.bak 16KB
elaborate.bat 422B
compile.bat 305B
simulate.bat 261B
runme.bat 229B
xsim.dbg 139KB
blk_mem_gen_0.dcp 57KB
blk_mem_gen_0.dcp 57KB
blk_mem_gen_0.dcp 57KB
compile.do 687B
compile.do 673B
compile.do 667B
compile.do 649B
simulate.do 341B
simulate.do 340B
simulate.do 340B
elaborate.do 213B
simulate.do 203B
wave.do 32B
wave.do 32B
wave.do 32B
wave.do 32B
simulate.do 11B
xsimk.exe 303KB
run.f 474B
usage_statistics_ext_xsim.html 3KB
.xsim_webtallk.info 64B
xsim.ini 16KB
xsim.ini 16KB
xsimSettings.ini 741B
vivado_10560.backup.jou 1KB
webtalk.jou 853B
webtalk_8080.backup.jou 853B
vivado.jou 749B
vivado_3320.backup.jou 741B
vivado.jou 723B
ISEWrap.js 7KB
rundef.js 1KB
vivado_10560.backup.log 72KB
elaborate.log 4KB
runme.log 4KB
runme.log 4KB
vivado.log 1KB
vivado_3320.backup.log 1KB
summary.log 985B
summary.log 985B
summary.log 985B
summary.log 985B
summary.log 985B
summary.log 985B
summary.log 985B
summary.log 985B
summary.log 985B
xvlog.log 969B
compile.log 969B
webtalk_8080.backup.log 922B
webtalk.log 922B
xsimkernel.log 312B
simulate.log 261B
xsimcrash.log 0B
project_3.lpr 290B
xsim.mem 23KB
elab.opt 218B
xelab.pb 8KB
vivado.pb 5KB
xvlog.pb 2KB
blk_mem_gen_0_utilization_synth.pb 289B
仿真图.png 116KB
tb_vlog.prj 462B
vlog.prj 142B
xsim.reloc 23KB
xil_defaultlib.rlx 605B
blk_mem_gen_0_utilization_synth.rpt 7KB
.vivado.begin.rst 179B
.vivado.end.rst 0B
.Vivado_Synthesis.queue.rst 0B
xsim.rtti 364B
blk_mem_gen_0.sdb 9KB
axi_ctrl.sdb 9KB
glbl.sdb 4KB
axi_top.sdb 3KB
tb.sdb 1KB
blk_mem_gen_0.sh 7KB
blk_mem_gen_0.sh 6KB
blk_mem_gen_0.sh 5KB
blk_mem_gen_0.sh 5KB
blk_mem_gen_0.sh 5KB
blk_mem_gen_0.sh 5KB
blk_mem_gen_0.sh 5KB
ISEWrap.sh 2KB
runme.sh 1KB
xsim.svtype 116B
xsim.svtype 8B
.blk_mem_gen_0_sim_netlist.v.swp 16KB
blk_mem_gen_0.tcl 8KB
xsim_webtalk.tcl 4KB
cmd.tcl 464B
tb.tcl 460B
blk_mem_gen_v8_3_changelog.txt 6KB
README.txt 3KB
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