IEEE MICROWAVE AND WIRELESS COMPONENTS LETTERS, VOL. 26, NO. 11, NOVEMBER 2016 921
A Linear InGaP/GaAs HBT Power Amplifier
Using Parallel-Combined Transistors
With IMD3 Cancellation
Seungjun Baek, Hyunjin Ahn, Ilku Nam, Namsik Ryu, Hui Dong Lee, Bonghyuk Park, and Ockgoo Lee
Abstract—In this letter, we present a linear InGaP/GaAs
HBT power amplifier (PA) with parallel-combined transistors
for small-cell applications. Ballast resistors with bypass resistors
and capacitors are employed in parallel-combined transistors.
When the resistors and capacitors are set to appropriate values,
IMD3 components of the parallel-combined transistors are found
to be out of phase with each other by 180
◦
and are canceled
out at the output. The experimental results show that the
proposed HBT PA with parallel-combined transistors produces
a saturated output power of 33.5 dBm at 0.88 GHz, with a
power-added efficiency (PAE) of 46.1% at a 5-V supply voltage.
To validate the effectiveness of the proposed HBT PA for
linearity improvement, the implemented PA is also tested with a
long-term evolution (LTE) signal (8.1-dB PAPR with 10-MHz
bandwidth). The proposed PA achieves an adjacent channel
leakage ratio (ACLR) below −45 dBc at an average power of
25.6 dBm with a PAE of 18.8% without applying predistortion.
Index Terms— InGaP/GaAs HBT, parallel-combined transis-
tors, power amplifier, small cell, third-order inter-modulation
distortion (IMD3).
I. INTRODUCTION
R
ECENTLY, the demand for small-cells such as
femtocells, picocells, and microcells has increased in
order to achieve an enormous data capacity and to meet
user the quality-of-service (QoS) requirements. Small cells
can provide a viable and cost-effective solution to improve
the cellular coverage, capacity, and applications for homes,
enterprises, as well as for metropolitan and rural areas [1].
Given that the base station power consumption is mostly
attributed to power amplifiers (PAs), a highly efficient PA
is required.
The InGaP/GaAs HBTs tend to offer high linearity, effi-
ciency, and harmonic performance at a relatively high power
level. Although lots of researches are dedicated to replac-
ing HBT-based PAs with CMOS PAs [2], HBT-based PAs
are currently dominating the market for wireless commu-
nication applications. However, the high peak-to-average
power ratio (PAPR) and high data bandwidth for a
fourth-generation standard, such as long-term evolution (LTE),
Manuscript received April 12, 2016; revised July 11, 2016; accepted
August 3, 2016. Date of publication October 31, 2016; date of current version
November 4, 2016. This work was supported by the IT R$D program of
MOTIE/KEIT [(10049443) Development of RF Transceiver including PA for
LTE-A Basestation]. The CAD tools were supported by IDEC.
S. Baek, H. Ahn, I. Nam, and O. Lee are with the Department of Electronic
Engineering and PNU-LG Electronics Smart Control Center, Pusan National
University, Busan, South Korea (e-mail: olee@pusan.ac.kr).
N. Ryu, H. D. Lee, and B. Park are with Mobile RF Team, Electronics and
Telecommunications Research Institute (ETRI), Daejeon, South Korea.
Color versions of one or more of the figures in this paper are available
online at http://ieeexplore.ieee.org.
Digital Object Identifier 10.1109/LMWC.2016.2615361
Fig. 1. Structure of the proposed parallel-combined transistors for IMD3
cancellation.
a highly linear operation is required. For example, femtocell
base station applications require strict linearity, and the specifi-
cation for adjacent channel leakage ratio (ACLR) performance
is required to be below −45 dBc [3].
To satisfy the strict linearity requirement, the PA is typically
operated in a large back-off power region from the saturated
power of the PA. This implies that the PA operates in a
low-efficiency region, thereby reducing the battery lifetime.
Thus, a highly linear operation is required to operate the
PA in a relatively small back-off power region. To improve
the linearity performance of InGaP/GaAs HBT-based PAs,
active bias circuits are typically used to compensate for the
distortion [4]–[6]. In addition, a dynamic feedback Darlington
structure has been proposed in [7]. In [8], resistors in the driver
and power stages of a two-stage configuration are adjusted so
that the generated IMD3 components by each stage cancel
each other out, resulting in the improvement of the IMD3
performance.
This study proposes an HBT PA with parallel-combined
transistors that exhibit an increased output power as well
as improved linearity performance, as shown in Fig. 1.
An out-of-phase relationship of IMD3 between parallel-
combined transistors can be obtained with proper selection of
resistors and capacitors in parallel-combined power cells with
active bias circuits. The linearity performances of the PA with
parallel-combined transistors can be improved by an IMD3
cancellation mechanism.
II. HBT PA W
ITH PARALLEL-COMBINED TRANSISTORS
Fig. 1 show a schematic of the parallel-combined power
cells with bias circuits. The bias circuit configuration con-
sists of two diode-connected transistors Q
4
and Q
5
, a lin-
earization capacitor C
bypass
, and an active bias transistor Q
3
.
The linearizing C
bypass
with the base-emitter diode transis-
1531-1309 © 2016 IEEE. Personal use is permitted, but republication/redistribution requires IEEE permission.
See http://www.ieee.org/publications_standards/publications/rights/index.html for more information.
Authorized licensed use limited to: NORTHWESTERN POLYTECHNICAL UNIVERSITY. Downloaded on September 08,2021 at 15:40:25 UTC from IEEE Xplore. Restrictions apply.
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