################################################################################
# Vivado (TM) v2018.3 (64-bit)
#
# README.txt: Please read the sections below to understand the steps required
# to simulate the design for a simulator, the directory structure
# and the generated exported files.
#
################################################################################
1. Simulate Design
To simulate design, cd to the simulator directory and execute the script.
For example:-
% cd questa
% ./top.sh
The export simulation flow requires the Xilinx pre-compiled simulation library
components for the target simulator. These components are referred using the
'-lib_map_path' switch. If this switch is specified, then the export simulation
will automatically set this library path in the generated script and update,
copy the simulator setup file(s) in the exported directory.
If '-lib_map_path' is not specified, then the pre-compiled simulation library
information will not be included in the exported scripts and that may cause
simulation errors when running this script. Alternatively, you can provide the
library information using this switch while executing the generated script.
For example:-
% ./top.sh -lib_map_path /design/questa/clibs
Please refer to the generated script header 'Prerequisite' section for more details.
2. Directory Structure
By default, if the -directory switch is not specified, export_simulation will
create the following directory structure:-
<current_working_directory>/export_sim/<simulator>
For example, if the current working directory is /tmp/test, export_simulation
will create the following directory path:-
/tmp/test/export_sim/questa
If -directory switch is specified, export_simulation will create a simulator
sub-directory under the specified directory path.
For example, 'export_simulation -directory /tmp/test/my_test_area/func_sim'
command will create the following directory:-
/tmp/test/my_test_area/func_sim/questa
By default, if -simulator is not specified, export_simulation will create a
simulator sub-directory for each simulator and export the files for each simulator
in this sub-directory respectively.
IMPORTANT: Please note that the simulation library path must be specified manually
in the generated script for the respective simulator. Please refer to the generated
script header 'Prerequisite' section for more details.
3. Exported script and files
Export simulation will create the driver shell script, setup files and copy the
design sources in the output directory path.
By default, when the -script_name switch is not specified, export_simulation will
create the following script name:-
<simulation_top>.sh (Unix)
When exporting the files for an IP using the -of_objects switch, export_simulation
will create the following script name:-
<ip-name>.sh (Unix)
Export simulation will create the setup files for the target simulator specified
with the -simulator switch.
For example, if the target simulator is "ies", export_simulation will create the
'cds.lib', 'hdl.var' and design library diectories and mappings in the 'cds.lib'
file.
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- 本资源为武汉大学计算机学院 计算机组成与设计课程实验项目 - 基于riscv流水线CPU设计的Verilog实现 - 主要实现了以下指令集: S1={sb, sh, sw, lb, lh, lw, lbu, lhu} S2={add,sub,xor, or, and, srl, sra, sll} S3={xori, ori, andi, srli, srai, slli} S4={slt, sltu, slti, sltiu} S5={jal, jalr} S6={beq, bne, blt, bge, bltu, bgeu} - 具有冒险检测与冲突解决功能 - 资源中存在Modelsim工程和Vivado工程
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RISC-V流水线CPU设计 (364个子文件)
__synthesis_is_complete__ 0B
__synthesis_is_complete__ 0B
_info 6KB
_vmake 29B
riscv32_sim1.asm 310B
riscv32_sim1.asm 310B
riscv32_sim5.asm 270B
riscv32_sim5.asm 270B
riscv32_forwarding_sim1.asm 240B
riscv32_forwarding_sim3.asm 190B
riscv32_sim2.asm 140B
riscv32_sim2.asm 140B
riscv32_sim3.asm 130B
riscv32_sim3.asm 130B
riscv32_sim4.asm 110B
riscv32_sim4.asm 110B
datapath.v.bak 10KB
controller.v.bak 7KB
function.v.bak 6KB
tancilon_defines.v.bak 3KB
riscv_pipeline.v.bak 2KB
riscv_tb.v.bak 2KB
regfile.v.bak 1010B
ram.v.bak 776B
alu.v.bak 2B
runme.bat 229B
runme.bat 229B
runme.bat 229B
IP2SOC_Top.bit 3.65MB
IP2SOC_Top-sortstudent.bit 3.65MB
IP2SOC_Top-fib.bit 3.65MB
sortstudent.bit 3.65MB
riscv-studentnosorting.coe 847B
riscv-studentnosorting.coe 757B
fibonacci.coe 271B
fibonacci.coe 271B
fibonacci.coe 271B
fibonacci.coe 271B
fibonacci.coe 271B
fibonacci.coe 271B
fibonacci.coe 271B
fibonacci.coe 271B
fibonacci.coe 271B
fibonacci.coe 271B
riscv32_sort_sim.dat 450B
IP2SOC_Top_routed.dcp 11.35MB
IP2SOC_Top_placed.dcp 8.38MB
IP2SOC_Top_opt.dcp 4.45MB
IP2SOC_Top.dcp 4.19MB
imem.dcp 25KB
imem.dcp 25KB
imem.dcp 19KB
imem.dcp 19KB
imem.dcp 19KB
compile.do 499B
compile.do 475B
compile.do 440B
compile.do 430B
simulate.do 318B
simulate.do 308B
simulate.do 308B
elaborate.do 190B
simulate.do 185B
wave.do 32B
wave.do 32B
wave.do 32B
wave.do 32B
simulate.do 11B
readme.docx 76KB
run.f 276B
run.f 264B
usage_statistics_webtalk.html 26KB
xsim.ini 22KB
vivado.jou 6KB
vivado_20068.backup.jou 713B
vivado.jou 713B
vivado_8004.backup.jou 712B
vivado.jou 708B
vivado.jou 699B
ISEWrap.js 7KB
ISEWrap.js 7KB
ISEWrap.js 7KB
rundef.js 1KB
rundef.js 1KB
rundef.js 1KB
runme.log 56KB
runme.log 32KB
runme.log 29KB
vivado.log 14KB
PCPU.lpr 343B
imem.mif 759B
imem.mif 759B
imem.mif 759B
imem.mif 759B
imem.mif 759B
imem.mif 759B
imem.mif 759B
imem.mif 759B
imem.mif 759B
imem.mif 759B
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