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Datasheet

www.renesas.com

Renesas RA2A1 Group

Datasheet

32-Bit MCU

Renesas Advanced (RA) Family

Renesas RA2 Series

Mar 2020Rev.1.10

All information contained in these materials, including products and product specifications,

represents information on the product at the time of publication and is subject to change by

Renesas Electronics Corp. without notice. Please review the latest information published by

Renesas Electronics Corp. through various means, including the Renesas Electronics Corp.

website (http://www.renesas.com).

Cover

Features

R01DS0354EJ0110 Rev.1.10 Page 2 of 100

Mar 16, 2020

■ Arm Cortex-M23 Core

 Armv8-M architecture

 Maximum operating frequency: 48 MHz

 Arm

Memory Protection Unit (Arm MPU) with 8 regions

 Debug and Trace: DWT, FPB, and CoreSight™ MTB-M23

 CoreSight Debug Port: SW-DP

■ Memory

 Up to 256-KB code flash memory

 8-KB data flash memory (100,000 program/erase (P/E) cycles)

 Up to 32-KB SRAM

 Flash Cache (FCACHE)

 Memory Protection Unit (MPU)

 Memory Mirror Function (MMF)

 128-bit unique ID

■ Connectivity

 USB 2.0 Full-Speed (USBFS) module

- On-chip transceiver with voltage regulator

- Compliant with USB Battery Charging Specification 1.2

 Serial Communications Interface (SCI) × 3

- UART

- Simple IIC

- Simple SPI

 Serial Peripheral Interface (SPI) × 2

 I

C bus interface (IIC) × 2

 Controller Area Network (CAN) module

■ Analog

 16-bit A/D Converter (ADC16)

- 1.2 Msps

- Differential input mode

- Single-ended input mode

 24-bit Sigma-Delta A/D Converter (SDADC24)

- 15.6 ksps

- Differential input mode

- Single-ended input mode

 12-bit D/A Converter (DAC12)

 8-bit D/A Converter (DAC8) × 2

 High-Speed Analog Comparator (ACMPHS)

 Low-Power Analog Comparator (ACMPLP) × 2

 Operational Amplifier (OPAMP) × 3

 Temperature Sensor (TSN)

■ Timers

 General PWM Timer 32-bit (GPT32)

 General PWM Timer 16-bit (GPT16) × 6

 Asynchronous General-Purpose Timer (AGT) × 2

 Watchdog Timer (WDT)

■ Safety

 Error Correction Code (ECC) in SRAM

 SRAM parity error check

 Flash area protection

 ADC self-diagnosis function

 Clock Frequency Accuracy Measurement Circuit (CAC)

 Cyclic Redundancy Check (CRC) calculator

 Data Operation Circuit (DOC)

 Port Output Enable for GPT (POEG)

 Independent Watchdog Timer (IWDT)

 GPIO readback level detection

 Register write protection

 Main oscillator stop detection

 Illegal memory access

■ System and Power Management

 Low power modes

 Realtime Clock (RTC)

 Event Link Controller (ELC)

 Data Transfer Controller (DTC)

 Key Interrupt Function (KINT)

 Power-on reset

 Low Voltage Detection (LVD) with voltage settings

■ Security and Encryption

 AES128/256

 True Random Number Generator (TRNG)

■ Human Machine Interface (HMI)

 Capacitive Touch Sensing Unit (CTSU)

■ Multiple Clock Sources

 Main clock oscillator (MOSC)

(1 to 20 MHz when VCC = 2.4 to 5.5 V)

(1 to 8 MHz when VCC = 1.8 to 5.5 V)

(1 to 4 MHz when VCC = 1.6 to 5.5 V)

 Sub-clock oscillator (SOSC) (32.768 kHz)

 High-speed on-chip oscillator (HOCO)

(24, 32, 48, 64 MHz when VCC = 2.4 to 5.5 V)

(24, 32, 48 MHz when VCC = 1.8 to 5.5 V)

(24, 32 MHz when VCC = 1.6 to 5.5 V)

 Middle-speed on-chip oscillator (MOCO) (8 MHz)

 Low-speed on-chip oscillator (LOCO) (32.768 kHz)

 IWDT-dedicated on-chip oscillator (15 kHz)

 Clock trim function for HOCO/MOCO/LOCO

 Clock out support

■ General Purpose I/O Ports

 Up to 49 input/output pins

- Up to 3 CMOS input

- Up to 46 CMOS input/output

- Up to 9 input/output 5 V tolerant

- Up to 3 high current (20 mA)

■ Operating Voltage

 VCC: 1.6 to 5.5 V

■ Operating Temperature and Packages

 Ta = -40°C to +85°C

- 36-pin BGA (5 mm × 5 mm, 0.8 mm pitch)

 Ta = -40°C to +105°C

- 64-pin LQFP (10 mm × 10 mm, 0.5 mm pitch)

- 32-pin LQFP (7 mm × 7 mm, 0.8 mm pitch)

- 48-pin QFN (7 mm × 7 mm, 0.5 mm pitch)

- 40-pin QFN (6 mm × 6 mm, 0.5 mm pitch)

Ultra-low power 48-MHz Arm

Cortex

-M23 core, up to 256-KB code flash memory, 32-KB SRAM, Capacitive Touch

Sensing Unit, 16-bit A/D Converter, 24-bit sigma-delta A/D Converter, 12-bit D/A Converter, 8-bit D/A Converter,

Operational Amplifier, security and safety features.

Features

RA2A1 Group

Datasheet

Features

R01DS0354EJ0110 Rev.1.10 Page 3 of 100

Mar 16, 2020

RA2A1 Datasheet 1. Overview

1. Overview

The MCU integrates multiple series of software- and pin-compatible Arm

-based 32-bit cores that share a common set

of Renesas peripherals to facilitate design scalability and efficient platform-based product development.

The MCU in this series incorporates an energy-efficient Arm Cortex

-M23 32-bit core that is particularly well suited for

cost-sensitive and low-power applications, with the following features:

 Up to 256-KB code flash memory

 32-KB SRAM

 16-bit A/D Converter (ADC16)

 24-bit Sigma-Delta A/D Converter (SDADC24)

 12-bit D/A Converter (DAC12)

 8-bit D/A Converter (DAC8)

 Operational Amplifier (OPAMP) with configurable switches

 Security features.

1.1 Function Outline

Table 1.1 Arm core

Feature Functional description

Arm Cortex-M23 core  Maximum operating frequency: up to 48 MHz

 Arm Cortex-M23 core:

- Revision: r1p0-00rel0

- Armv8-M architecture profile

- Single-cycle integer multiplier

- 17-cycle integer divider.

 Arm Memory Protection Unit (Arm MPU):

- Armv8 Protected Memory System Architecture

- 8 protect regions.

 SysTick timer:

- Driven by SYSTICCLK (LOCO) or ICLK.

Table 1.2 Memory

Feature Functional description

Code flash memory 256 KB of code flash memory. See section 43, Flash Memory in User’s Manual.

Data flash memory 8 KB of data flash memory. See section 43, Flash Memory in User’s Manual.

Memory Mirror Function (MMF) The Memory Mirror Function (MMF) can be configured to mirror the desired application image

load address in code flash memory to the application image link address in the 23-bit unused

memory space (memory mirror space addresses). Your application code is developed and

linked to run from this MMF destination address. Your application code does not need to know

the load location where it is stored in code flash memory. See section 5, Memory Mirror

Function (MMF) in User’s Manual.

Option-setting memory The option-setting memory determines the state of the MCU after a reset. See section 7,

Option-Setting Memory in User’s Manual.

SRAM On-chip high-speed SRAM with either parity bit or Error Correction Code (ECC). See section

42, SRAM in User’s Manual.

Table 1.3 System (1 of 2)

Feature Functional description

Operating modes Two operating modes:

 Single-chip mode

 SCI or USB boot mode.

See section 3, Operating Modes in User’s Manual.

R01DS0354EJ0110 Rev.1.10 Page 4 of 100

Mar 16, 2020

RA2A1 Datasheet 1. Overview

Resets 13 resets:

 RES pin reset

 Power-on reset

 Independent watchdog timer reset

 Watchdog timer reset

 Voltage monitor 0 reset

 Voltage monitor 1 reset

 Voltage monitor 2 reset

 SRAM parity error reset

 SRAM ECC error reset

 Bus master MPU error reset

 Bus slave MPU error reset

 CPU stack pointer error reset

 Software reset.

See section 6, Resets in User’s Manual.

Low Voltage Detection (LVD) The Low Voltage Detection (LVD) function monitors the voltage level input to the VCC pin and

the detection level can be selected using a software program. See section 8, Low Voltage

Detection (LVD) in User’s Manual.

Clocks  Main clock oscillator (MOSC)

 Sub-clock oscillator (SOSC)

 High-speed on-chip oscillator (HOCO)

 Middle-speed on-chip oscillator (MOCO)

 Low-speed on-chip oscillator (LOCO)

 IWDT-dedicated on-chip oscillator

 Clock out support.

See section 9, Clock Generation Circuit in User’s Manual.

Clock Frequency Accuracy

Measurement Circuit (CAC)

The Clock Frequency Accuracy Measurement Circuit (CAC) counts pulses of the clock to be

measured (measurement target clock) within the time generated by the clock to be used as a

measurement reference (measurement reference clock), and determines the accuracy

depending on whether the number of pulses is within the allowable range.

When measurement is complete or the number of pulses within the time generated by the

measurement reference clock is not within the allowable range, an interrupt request is

generated. See section 10, Clock Frequency Accuracy Measurement Circuit (CAC) in User’s

Manual.

Interrupt Controller Unit (ICU) The Interrupt Controller Unit (ICU) controls which event signals are linked to the NVIC/DTC

module. The ICU also controls NMI interrupts. See section 13, Interrupt Controller Unit (ICU) in

User’s Manual.

Key Interrupt Function (KINT) A key interrupt can be generated by setting the Key Return Mode Register (KRM) and inputting

a rising or falling edge to the key interrupt input pins. See section 19, Key Interrupt Function

(KINT) in User’s Manual.

Low power modes Power consumption can be reduced in multiple ways, such as by setting clock dividers,

stopping modules, selecting power control mode in normal operation, and transitioning to low

power modes. See section 11, Low Power Modes in User’s Manual.

Register write protection The register write protection function protects important registers from being overwritten due to

software errors. See section 12, Register Write Protection in User’s Manual.

Memory Protection Unit (MPU) Four Memory Protection Units (MPUs) and a CPU stack pointer monitor function are provided

for memory protection. See section 15, Memory Protection Unit (MPU) in User’s Manual.

Watchdog Timer (WDT) The Watchdog Timer (WDT) is a 14-bit down-counter that can be used to reset the MCU when

the counter underflows because the system has run out of control and is unable to refresh the

WDT. In addition, a non-maskable interrupt or interrupt can be generated by an underflow. A

refresh-permitted period can be set to refresh the counter and used as the condition to detect

when the system runs out of control. See section 24, Watchdog Timer (WDT) in User’s

Manual.

Independent Watchdog Timer (IWDT) The Independent Watchdog Timer (IWDT) consists of a 14-bit down-counter that must be

serviced periodically to prevent counter underflow. The IWDT provides functionality to reset

the MCU or to generate a non-maskable interrupt/interrupt for a timer underflow. Because the

timer operates with an independent, dedicated clock source, it is particularly useful in returning

the MCU to a known state as a fail-safe mechanism when the system runs out of control. The

IWDT can be triggered automatically on a reset, underflow, refresh error, or by a refresh of the

count value in the registers. See section 25, Independent Watchdog Timer (IWDT) in User’s

Manual.

Table 1.3 System (2 of 2)

Feature Functional description

R01DS0354EJ0110 Rev.1.10 Page 5 of 100

Mar 16, 2020

RA2A1 Datasheet 1. Overview

Table 1.4 Event Link

Feature Functional description

Event Link Controller (ELC) The Event Link Controller (ELC) uses the interrupt requests generated by various peripheral

modules as event signals to connect them to different modules, enabling direct interaction

between the modules without CPU intervention. See section 17, Event Link Controller (ELC) in

User’s Manual.

Table 1.5 Direct memory access

Feature Functional description

Data Transfer Controller (DTC) A Data Transfer Controller (DTC) module is provided for transferring data when activated by an

interrupt request. See section 16, Data Transfer Controller (DTC) in User’s Manual.

Table 1.6 Timers

Feature Functional description

General PWM Timer (GPT) The General PWM Timer (GPT) is a 32-bit timer with one channel and a 16-bit timer with six

channels. PWM waveforms can be generated by controlling the up-counter, down-counter, or

the up- and down-counter. In addition, PWM waveforms can be generated for controlling

brushless DC motors. The GPT can also be used as a general-purpose timer. See section 21,

General PWM Timer (GPT) in User’s Manual.

Port Output Enable for GPT (POEG) Use the Port Output Enable for GPT (POEG) function to place the General PWM Timer (GPT)

output pins in the output disable state. See section 20, Port Output Enable for GPT (POEG) in

User’s Manual.

Asynchronous General Purpose

Timer (AGT)

The Asynchronous General Purpose Timer (AGT) is a 16-bit timer that can be used for pulse

output, external pulse width or period measurement, and counting external events.

This 16-bit timer consists of a reload register and a down-counter. The reload register and the

down-counter are allocated to the same address, and they can be accessed with the AGT

Realtime Clock (RTC) The Realtime Clock (RTC) has two counting modes, calendar count mode and binary count

mode, that are controlled by the register settings.

For calendar count mode, the RTC has a 100-year calendar from 2000 to 2099 and

automatically adjusts dates for leap years.

For binary count mode, the RTC counts seconds and retains the information as a serial value.

Binary count mode can be used for calendars other than the Gregorian (Western) calendar.

See section 23, Realtime Clock (RTC) in User’s Manual.

Table 1.7 Communication interfaces (1 of 2)

Feature Functional description

Serial Communications Interface

(SCI)

The Serial Communication Interface (SCI) is configurable to five asynchronous and

synchronous serial interfaces:

 Asynchronous interfaces (UART and asynchronous communications interface adapter

(ACIA))

 8-bit clock synchronous interface

 Simple IIC (master-only)

 Simple SPI

 Smart card interface.

The smart card interface complies with the ISO/IEC 7816-3 standard for electronic signals and

transmission protocol.

SCI0 has FIFO buffers to enable continuous and full-duplex communication, and the data

transfer speed can be configured independently using an on-chip baud rate generator. See

section 27, Serial Communications Interface (SCI) in User’s Manual.

C bus interface (IIC) The 2-channel I

C bus interface (IIC) conforms with and provides a subset of the NXP I

(Inter-Integrated Circuit) bus interface functions. See section 28, I2C Bus Interface (IIC) in

User’s Manual.

Serial Peripheral Interface (SPI) Two independent Serial Peripheral Interface (SPI) channels are capable of high-speed, full-

duplex synchronous serial communications with multiple processors and peripheral devices.

See section 30, Serial Peripheral Interface (SPI) in User’s Manual.

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