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Datasheet

R01DS0261EJ0120 Rev.1.20 Page 1 of 170

Sep 28, 2018

RX230 Group, RX231 Group

Renesas MCUs

Features

■ 32-bit RXv2 CPU core

• Max. operating frequency: 54 MHz

Capable of 88.56 DMIPS in operation at 54 MHz

• Enhanced DSP: 32-bit multiply-accumulate and 16-bit

multiply-subtract instructions supported

• Built-in FPU: 32-bit single-precision floating point (compliant to

IEEE754)

• Divider (fastest instruction execution takes two CPU clock cycles)

• Fast interrupt

• CISC Harvard architecture with 5-stage pipeline

• Variable-length instructions, ultra-compact code

• On-chip debugging circuit

• Memory protection unit (MPU) supported

■ Low power design and architecture

• Operation from a single 1.8-V to 5.5-V supply

• RTC capable of operating on the battery backup power supply

• Three low power consumption modes

• Low power timer (LPT) that operates during the software standby state

■ On-chip flash memory for code

• 128- to 512-Kbyte capacities

• On-board or off-board user programming

• Programmable at 1.8 V

• For instructions and operands

■ On-chip data flash memory

• 8 Kbytes (1,000,000 program/erase cycles (typ.))

• BGO (Background Operation)

■ On-chip SRAM, no wait states

• 32- to 64-Kbyte size capacities

■ Data transfer functions

• DMAC: Incorporates four channels

• DTC: Four transfer modes

■ ELC

• Module operation can be initiated by event signals without using

interrupts.

• Linked operation between modules is possible while the CPU is sleeping.

■ Reset and supply management

• Eight types of reset, including the power-on reset (POR)

• Low voltage detection (LVD) with voltage settings

■ Clock functions

• Main clock oscillator frequency: 1 to 20 MHz

• External clock input frequency: Up to 20 MHz

• Sub-clock oscillator frequency: 32.768 kHz

• PLL circuit input: 4 MHz to 12.5 MHz

• On-chip low- and high-speed oscillators, dedicated on-chip low-speed

oscillator for the IWDT

• USB-dedicated PLL circuit: 4, 6, 8, or 12 MHz

54 MHz can be set for the system clock and 48 MHz for the USB clock

• Generation of a dedicated 32.768-kHz clock for the RTC

• Clock frequency accuracy measurement circuit (CAC)

■ Realtime clock

• Adjustment functions (30 seconds, leap year, and error)

• Calendar count mode or binary count mode selectable

• Time capture function

• Time capture on event-signal input through external pins

■ Independent watchdog timer

• 15-kHz on-chip oscillator produces a dedicated clock signal to drive

IWDT operation.

■ Useful functions for IEC60730 compliance

• Self-diagnostic and disconnection-detection assistance functions for

the A/D converter, clock frequency accuracy measurement circuit,

independent watchdog timer, RAM test assistance functions using the

DOC, etc.

■ External address space

• Four CS areas (4 × 16 Mbytes)

• 8- or 16-bit bus space is selectable per area

■ MPC

• Input/output functions selectable from multiple pins

■ Up to 14 communication functions

• USB 2.0 host/function/On-The-Go (OTG) (one channel),

full-speed = 12 Mbps, low-speed = 1.5 Mbps, isochronous transfer, and

BC (Battery Charger) supported

• CAN (one channel) compliant to ISO11898-1:

Transfer at up to 1 Mbps

• SCI with many useful functions (up to 7 channels)

Asynchronous mode, clock synchronous mode, smart card interface

Reduction of errors in communications using the bit modulation

function

• IrDA interface (one channel, in cooperation with the SCI5)

• I

C bus interface: Transfer at up to 400 kbps, capable of SMBus

operation (one channel)

• RSPI (one channel): Transfer at up to 16 Mbps

• Serial sound interface (one channel)

• SD host interface (optional: one channel) SD memory/ SDIO 1-bit or

4-bit SD bus supported

■ Up to 20 extended-function timers

• 16-bit MTU: input capture, output compare, complementary PWM

output, phase counting mode (six channels)

• 16-bit TPU: input capture, output compare, phase counting mode (six

channels)

• 8-bit TMR (four channels)

• 16-bit compare-match timers (four channels)

■ 12-bit A/D converter

• Capable of conversion within 0.83 μs

• 24 channels

• Sampling time can be set for each channel

• Self-diagnostic function and analog input disconnection detection

assistance function

■ 12-bit D/A converter

• Two channels

■ Capacitive touch sensing unit

• Self-capacitance method: A single pin configures a single key,

supporting up to 24 keys

• Mutual capacitance method: Matrix configuration with 24 pins, supporting

up to 144 keys

■ Analog comparator

• Two channels × two units

■ General I/O ports

• 5-V tolerant, open drain, input pull-up, switching of driving capacity

■ Encryption Functions (TSIP-Lite)

• Unauthorized access to the encryption engine is disabled and

imposture and falsification of information are prevented

• Safe management of keys

• 128- or 256-bit key length of AES for ECB, CBC, GCM, others

• True random number generator

■ Temperature sensor

■ Operating temperature range

•−40 to +85°C

•−40 to +105°C

■ Applications

• General industrial and consumer equipment

PLQP0100KB-B 14 × 14 mm, 0.5 mm pitch

PLQP0064KB-C 10 × 10 mm, 0.5 mm pitch

PLQP0048KB-B 7 × 7 mm, 0.5 mm pitch

PWQN0064KC-A 9 × 9 mm, 0.5 mm pitch

PWQN0048KB-A 7 × 7 mm, 0.5 mm pitch

PTLG0100KA-A 5.5 × 5.5 mm, 0.5 mm pitch

PWLG0064KA-A 5 × 5 mm, 0.5 mm pitch

54-MHz 32-bit RX MCUs, built-in FPU, 88.56 DMIPS, up to 512-KB flash memory,

various communication functions including USB 2.0 full-speed host/function/OTG, CAN, SD host

interface, serial sound interface, capacitive touch sensing unit, 12-bit A/D, 12-bit D/A, RTC, Encryption

functions

R01DS0261EJ0120

Rev.1.20

Sep 28, 2018

R01DS0261EJ0120 Rev.1.20 Page 2 of 170

Sep 28, 2018

RX230 Group, RX231 Group 1. Overview

1. Overview

1.1 Outline of Specifications

Table 1.1 lists the specifications, and Table 1.2 gives a comparison of the functions of the products in different

packages.

Table 1.1 is for products with the greatest number of functions, so the number of peripheral modules and channels will

differ in accordance with the package type. For details, see Table 1.2, Comparison of Functions for Different

Packages.

Table 1.1 Outline of Specifications (1/4)

Classification Module/Function Description

CPU CPU

• Maximum operating frequency: 54 MHz

• 32-bit RX CPU (RX v2)

• Minimum instruction execution time: One instruction per clock cycle

• Address space: 4-Gbyte linear

• Register set

General purpose: Sixteen 32-bit registers

Control: Ten 32-bit registers

Accumulator: Two 72-bit registers

• Basic instructions: 75 (variable-length instruction format)

• Floating-point instructions: 11

• DSP instructions: 23

• Addressing modes: 10

• Data arrangement

Instructions: Little endian

Data: Selectable as little endian or big endian

• On-chip 32-bit multiplier: 32-bit × 32-bit → 64-bit

• On-chip divider: 32-bit ÷ 32-bit → 32 bits

• Barrel shifter: 32 bits

• Memory protection unit (MPU)

FPU

• Single precision (32-bit) floating point

• Data types and floating-point exceptions in conformance with the IEEE754 standard

Memory ROM

• Capacity: 128/256/384/512 Kbytes

• Up to 32 MHz: No-wait memory access

32 to 54 MHz: Wait state required. No wait state if the instruction is served by a ROM accelerator hit.

• Programming/erasing method:

Serial programming (asynchronous serial communication/USB communication), self-programming

RAM

• Capacity: 32/64 Kbytes

• 54 MHz, no-wait memory access

E2 DataFlash

• Capacity: 8 Kbytes

• Number of erase/write cycles: 1,000,000 (typ)

MCU operating mode Single-chip mode, on-chip ROM enabled expansion mode, and on-chip ROM disabled expansion mode

(software switching)

Clock Clock generation circuit

• Main clock oscillator, sub-clock oscillator, low-speed on-chip oscillator, high-speed on-chip oscillator,

PLL frequency synthesizer, USB-dedicated PLL frequency synthesizer, and IWDT-dedicated on-chip

oscillator

• Oscillation stop detection: Available

• Clock frequency accuracy measurement circuit (CAC)

• Independent settings for the system clock (ICLK), peripheral module clock (PCLK), external bus clock

(BCLK), and FlashIF clock (FCLK)

The CPU and system sections such as other bus masters run in synchronization with the system

clock (ICLK): 54 MHz (at max.)

MTU2a runs in synchronization with the PCLKA: 54 MHz (at max.)

The ADCLK for the S12AD runs in synchronization with the PCLKD: 54 MHz (at max.)

Peripheral modules other than MTU2a and S12ADE run in synchronization with the PCLKB: 32 MHz

(at max.)

Devices connected to external buses run in synchronization with the BCLK: 32 MHz (at max.)

The flash peripheral circuit runs in synchronization with the FCLK: 32 MHz (at max.)

Resets RES# pin reset, power-on reset, voltage monitoring reset, watchdog timer reset, independent watchdog

timer reset, and software reset

Voltage detection Voltage detection circuit

(LVDAb)

• When the voltage on VCC falls below the voltage detection level, an internal reset or internal interrupt

is generated.

Vol

age detection circuit 0 is capable of selecting the detection voltage from 4 levels

Voltage detection circuit 1 is capable of selecting the detection voltage from 14 levels

Voltage detection circuit 2 is capable of selecting the detection voltage from 4 levels

R01DS0261EJ0120 Rev.1.20 Page 3 of 170

Sep 28, 2018

RX230 Group, RX231 Group 1. Overview

Low power

consumption

Low power consumption

functions

• Module stop function

• Three low power consumption modes

Sleep mode, deep sleep mode, and software standby mode

• Low power timer that operates during the software standby state

Function for lower operating

power consumption

• Operating power control modes

High-speed operating mode, middle-speed operating mode, and low-speed operating mode

Interrupt Interrupt controller (ICUb)

• Interrupt vectors: 167

• External interrupts: 9 (NMI, IRQ0 to IRQ7 pins)

• Non-maskable interrupts: 7 (NMI pin, oscillation stop detection interrupt, voltage monitoring 1

interrupt, voltage monitoring 2 interrupt, WDT interrupt, IWDT interrupt, and VBATT power monitoring

interrupt)

• 16 levels specifiable for the order of priority

External bus extension

• The external address space can be divided into four areas (CS0 to CS3), each with independent

control of access settings.

Capacity of each area: 16 Mbytes (CS0 to CS3)

A chip-select signal (CS0# to CS3#) can be output for each area.

Each area is specifiable as an 8-bit or 16-bit bus space

The data arrangement in each area is selectable as little or big endian (only for data).

Bus format: Separate bus, multiplex bus

• Wait control

• Write buffer facility

DMA DMA controller (DMACA)

• 4 channels

• Three transfer modes: Normal transfer, repeat transfer, and block transfer

• Activation sources: Software trigger, external interrupts, and interrupt requests from peripheral

functions

Data transfer controller

(DTCa)

• Transfer modes: Normal transfer, repeat transfer, and block transfer

• Activation sources: Interrupts

• Chain transfer function

I/O ports General I/O ports 100-pin/64-pin/48-pin

I/O: 79/43/30

(RX231 Group), 83/47/34 (RX230 Group)

• Input: 1/1/1

Pull-up resistors: 79/43/30(RX231 Group), 83/47/34 (RX230 Group)

• Open-drain outputs: 58/34/26

• 5-V tolerance: 8/5/5

Event link controller (ELC)

• Event signals of 61 types can be directly connected to the module

• Operations of timer modules are selectable at event input

• Capable of event link operation for port B and port E

Multi-function pin controller (MPC) Capable of selecting the input/output function from multiple pins

Timers 16-bit timer pulse unit

(TPUa)

• (16 bits × 6 channels) × 1 unit

• Maximum of 16 pulse-input/output possible

• Select from among seven or eight counter-input clock signals for each channel

• Supports the input capture/output compare function

• Output of PWM waveforms in up to 15 phases in PWM mode

• Support for buffered operation, phase-counting mode (two-phase encoder input) and cascade

connected operation (32 bits × 2 channels) depending on the channel.

• Capable of generating conversion start triggers for the A/D converters

• Signals from the input capture pins are input via a digital filter

• Clock frequency measuring method

Multi-function timer pulse

unit 2 (MTU2a)

• (16 bits × 6 channels) × 1 unit

• Up to 16 pulse-input/output lines and three pulse-input lines are available based on the six 16-bit

timer channels

• Select from among eight or seven counter-input clock signals for each channel (PCLK/1, PCLK/4,

PCLK/16, PCLK/64, PCLK/256, PCLK/1024, MTCLKA, MTCLKB, MTCLKC, MTCLKD) other than

channel 5, for which only four signals are available.

• Input capture function

• 21 output compare/input capture registers

• Pulse output mode

• Complementary PWM output mode

• Reset synchronous PWM mode

• Phase-counting mode

• Capable of generating conversion start triggers for the A/D converter

Port output enable 2

(POE2a)

Controls the high-impedance state of the MTU’s waveform output pins

Compare match timer

(CMT)

• (16 bits × 2 channels) × 2 units

• Select from among four clock signals (PCLK/8, PCLK/32, PCLK/128, PCLK/512)

Watchdog timer (WDTA)

• 14 bits x 1 channel

• Select from among six counter-input clock signals (PCLK/4, PCLK/64, PCLK/128, PCLK/512, PCLK/

2048, PCLK/8192)

Table 1.1 Outline of Specifications (2/4)

Classification Module/Function Description

R01DS0261EJ0120 Rev.1.20 Page 4 of 170

Sep 28, 2018

RX230 Group, RX231 Group 1. Overview

Timers

Independent watchdog

timer (IWDTa)

• 14 bits × 1 channel

• Count clock: Dedicated low-speed on-chip oscillator for the IWDT

Frequency divided by 1, 16, 32, 64, 128, or 256

Realtime clock (RTCe)

• Clock source: Sub-clock

• Time/calendar

• Interrupts: Alarm interrupt, periodic interrupt, and carry interrupt

• Time-capture facility for three values

Low power timer (LPT)

• 16 bits × 1 channel

• Clock source: Sub-clock, Dedicated low-speed on-chip oscillator for the IWDT

Frequency divided by 2, 4, 8, 16, or 32

8-bit timer (TMR)

• (8 bits × 2 channels) × 2 units

• Seven internal clocks (PCLK/1, PCLK/2, PCLK/8, PCLK/32, PCLK/64, PCLK/1024, and PCLK/8192)

and an external clock can be selected

• Pulse output and PWM output with any duty cycle are available

• Two channels can be cascaded and used as a 16-bit timer

Communication

functions

Serial communications

interfaces (SCIg, SCIh)

• 7 channels (channel 0, 1, 5, 6, 8, 9: SCIg, channel 12: SCIh)

• SCIg

Serial communications modes: Asynchronous, clock synchronous, and smart-card interface

Multi-processor function

On-chip baud rate generator allows selection of the desired bit rate

Choice of LSB-first or MSB-first transfer

Average transfer rate clock can be input from TMR timers for SCI5, SCI6, and SCI12

Start-bit detection: Level or edge detection is selectable.

Simple I

Simple SPI

9-bit transfer mode

Bit rate modulation

Event linking by the ELC (only on channel 5)

• SCIh (The following functions are added to SCIg)

Supports the serial communications protocol, which contains the start frame and information frame

Supports the LIN format

IrDA interface (IRDA)

• 1 channel (SCI5 used)

• Supports encoding/decoding of waveforms conforming to IrDA standard 1.0

C bus interface (RIICa)

• 1 channel

• Communications formats: I

C bus format/SMBus format

• Master mode or slave mode selectable

• Supports fast mode

Serial peripheral interface

(RSPIa)

• 1 channel

• Transfer facility

Using the MOSI (master out, slave in), MISO (master in, slave out), SSL (slave select), and RSPCK

(RSPI clock) enables serial transfer through SPI operation (four lines) or clock-synchronous

operation (three lines)

• Capable of handling serial transfer as a master or slave

• Data formats

• Choice of LSB-first or MSB-first transfer

The number of bits in each transfer can be changed to 8, 9, 10, 11, 12, 13, 14, 15, 16, 20, 24, or

32 bits.

128-bit buffers for transmission and reception

Up to four frames can be transmitted or received in a single transfer operation (with each frame

having up to 32 bits)

• Double buffers for both transmission and reception

USB 2.0 host/function

module (USBd)

• USB Device Controller (UDC) and transceiver for USB 2.0 are incorporated.

• Host/function module: 1 port

• Compliant with USB version 2.0

• Transfer speed: Full-speed (12 Mbps), low-speed (1.5 Mbps)

• OTG (ON-The-Go) is supported.

• Isochronous transfer is supported.

• BC1.2 (Battery Charging Specification Revision 1.2) is supported.

• Internal power supply for USB (allows operation without external power input to the VCC_USB pin

when VCC = 4.0 to 5.5V)

CAN module (RSCAN)

• 1 channel

• Compliance with the ISO11898-1 specification (standard frame and extended frame)

• 16 Message boxes

Table 1.1 Outline of Specifications (3/4)

Classification Module/Function Description

R01DS0261EJ0120 Rev.1.20 Page 5 of 170

Sep 28, 2018

RX230 Group, RX231 Group 1. Overview

Communication

functions

Serial Sound Interface (SSI)

• 1 channel

• Capable of duplex communications

• Various serial audio formats supported

• Master/slave function supported

• Programmable word clock or bit clock generation function

• 8/16/18/20/22/24/32-bit data formats supported

• On-chip 8-stage FIFO for transmission/reception

• Supports WS continue mode in which the SSIWS signal is not stopped.

SD Host Interface (SDHIa)

• 1 channel

• Transfer speed : Default speed mode (8MB/s)

• SD memory card interface (1 bit / 4bits SD bus)

• MMC, eMMC Backward-compatible are supported.

• SD Specifications

Part 1: Compliant with Physical Layer Specification Ver.3.01 (Not support DDR)

Part E1: SDIO Specification Ver. 3.00

• Error check function: CRC7 (command), CRC16 (data)

• Interrupt Source: Card access interrupt, SDIO access interrupt, Card detection interrupt,

SD buffer

access interrupt

• DMA transfer sources: SD_BUF write, SD_BUF read

• Card detection, Write protection

Encryption

functions

Trusted Secure IP (TSIP-

Lite)

• Access management circuit

• Encryption engine

128- or 256-bit key sizes of AES

Block cipher mode of operation: GCM, ECB, CBC, CMAC, XTS, CTR, GCTR

• Hash function

• True random number generator

• Prevention from illicit copying of a key

12-bit A/D converter (S12ADE)

• 12 bits (24 channels × 1 unit)

• 12-bit resolution

• Minimum conversion time: 0.83 µs per channel when the ADCLK is operating at 54 MHz

• Operating modes

Scan mode (single scan mode, continuous scan mode, and group scan mode)

Group A priority control (only for group scan mode)

• Sampling variable

Sampling time can be set up for each channel.

• Self-diagnostic function

• Double trigger mode (A/D conversion data duplicated)

• Detection of analog input disconnection

• A/D conversion start conditions

A software trigger, a trigger from a timer (MTU, TPU), an external trigger signal, or ELC

• Event linking by the ELC

Temperature sensor (TEMPSA)

• 1 channel

• The voltage output from the temperature sensor is converted into a digital value by the 12-bit A/D

converter.

12-bit D/A converter (R12DAA)

• 2 channels

• 12-bit resolution

• Output voltage: 0.4 to AVCC0-0.5V

CRC calculator (CRC)

• CRC code generation for arbitrary amounts of data in 8-bit units

• Select any of three generating polynomials:

+ X

+ X + 1, X

+ X

+ 1, or X

+ X

+ 1

• Generation of CRC codes for use with LSB-first or MSB-first communications is selectable.

Comparator B (CMPBa)

• 2 channels × 2 units

• Function to compare the reference voltage and the analog input voltage

• Window comparator operation or standard comparator operation is selectable

Capacitive touch sensing unit (CTSU) Detection pin: 24 channels

Data operation circuit (DOC) Comparison, addition, and subtraction of 16-bit data

Power supply voltages/Operating frequencies VCC = 1.8 to 2.4 V: 8 MHz, VCC = 2.4 to 2.7 V: 16 MHz, VCC = 2.7 to 5.5 V: 54 MHz

Operating temperature range D version: −40 to +85°C, G version: −40 to +105°C

Packages 100-pin TFLGA (PTLG0100KA-A) 5.5 × 5.5 mm, 0.5 mm pitch

100-pin LFQFP (PLQP0100KB-B) 14 × 14 mm, 0.5 mm pitch

64-pin WFLGA (PWLG0064KA-A) 5 × 5 mm, 0.5 mm pitch

64-pin HWQFN (PWQN0064KC-A) 9 × 9 mm, 0.5 mm pitch

64-pin LFQFP (PLQP0064KB-C) 10 × 10 mm, 0.5 mm pitch

48-pin HWQFN (PWQN0048KB-A) 7 × 7 mm, 0.5 mm pitch

48-pin LFQFP (PLQP0048KB-B) 7 × 7 mm, 0.5 mm pitch

Debugging interfaces FINE interface

Table 1.1 Outline of Specifications (4/4)

Classification Module/Function Description

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