2015电赛F题频率计FPGA等精度测频verilog占空比时间间隔

， PLL为锁相环倍频， top为顶层文件， uartsent为串口发送模块，与tx_module文件夹一起， measure为测量模块，测频采用等精度法，测占空比采用多次平均，时间间隔采用多次平均。 仍有更多方法，由于比赛时间仓促未能完成。有兴趣的可以联系交流 系统由单片机控制触发一次测量。 V1为固定间隔时间1s的1s闸门 V2为下降沿触发 V3单片机下降沿触发 ============================================================================================ /* * TONY-NING * All Rights Reserved. * * File name: * File description: Measure the frequency and duty and time * Operating environment: QUARTUS II 13.0,cyclone II EP2C8Q208C8N * * This version: 1.0 * Author: tonyning (ning.pg@qq.com) * Previous Author: none * Complete date: 2015-09-5 * other: if you want to get more information or get some guide,you can contact author by E-mail */