/******************************************************************************
* Copyright (C) 2010-2020 <Xilinx Inc.>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License along
* with this program; if not, see <http://www.gnu.org/licenses/>
*
*
******************************************************************************/
/****************************************************************************/
/**
*
* @file ps7_init_gpl.c
*
* This file is automatically generated
*
*****************************************************************************/
#include "ps7_init_gpl.h"
unsigned long ps7_pll_init_data_3_0[] = {
// START: top
// .. START: SLCR SETTINGS
// .. UNLOCK_KEY = 0XDF0D
// .. ==> 0XF8000008[15:0] = 0x0000DF0DU
// .. ==> MASK : 0x0000FFFFU VAL : 0x0000DF0DU
// ..
EMIT_WRITE(0XF8000008, 0x0000DF0DU),
// .. FINISH: SLCR SETTINGS
// .. START: PLL SLCR REGISTERS
// .. .. START: ARM PLL INIT
// .. .. PLL_RES = 0x2
// .. .. ==> 0XF8000110[7:4] = 0x00000002U
// .. .. ==> MASK : 0x000000F0U VAL : 0x00000020U
// .. .. PLL_CP = 0x2
// .. .. ==> 0XF8000110[11:8] = 0x00000002U
// .. .. ==> MASK : 0x00000F00U VAL : 0x00000200U
// .. .. LOCK_CNT = 0xfa
// .. .. ==> 0XF8000110[21:12] = 0x000000FAU
// .. .. ==> MASK : 0x003FF000U VAL : 0x000FA000U
// .. ..
EMIT_MASKWRITE(0XF8000110, 0x003FFFF0U ,0x000FA220U),
// .. .. .. START: UPDATE FB_DIV
// .. .. .. PLL_FDIV = 0x28
// .. .. .. ==> 0XF8000100[18:12] = 0x00000028U
// .. .. .. ==> MASK : 0x0007F000U VAL : 0x00028000U
// .. .. ..
EMIT_MASKWRITE(0XF8000100, 0x0007F000U ,0x00028000U),
// .. .. .. FINISH: UPDATE FB_DIV
// .. .. .. START: BY PASS PLL
// .. .. .. PLL_BYPASS_FORCE = 1
// .. .. .. ==> 0XF8000100[4:4] = 0x00000001U
// .. .. .. ==> MASK : 0x00000010U VAL : 0x00000010U
// .. .. ..
EMIT_MASKWRITE(0XF8000100, 0x00000010U ,0x00000010U),
// .. .. .. FINISH: BY PASS PLL
// .. .. .. START: ASSERT RESET
// .. .. .. PLL_RESET = 1
// .. .. .. ==> 0XF8000100[0:0] = 0x00000001U
// .. .. .. ==> MASK : 0x00000001U VAL : 0x00000001U
// .. .. ..
EMIT_MASKWRITE(0XF8000100, 0x00000001U ,0x00000001U),
// .. .. .. FINISH: ASSERT RESET
// .. .. .. START: DEASSERT RESET
// .. .. .. PLL_RESET = 0
// .. .. .. ==> 0XF8000100[0:0] = 0x00000000U
// .. .. .. ==> MASK : 0x00000001U VAL : 0x00000000U
// .. .. ..
EMIT_MASKWRITE(0XF8000100, 0x00000001U ,0x00000000U),
// .. .. .. FINISH: DEASSERT RESET
// .. .. .. START: CHECK PLL STATUS
// .. .. .. ARM_PLL_LOCK = 1
// .. .. .. ==> 0XF800010C[0:0] = 0x00000001U
// .. .. .. ==> MASK : 0x00000001U VAL : 0x00000001U
// .. .. ..
EMIT_MASKPOLL(0XF800010C, 0x00000001U),
// .. .. .. FINISH: CHECK PLL STATUS
// .. .. .. START: REMOVE PLL BY PASS
// .. .. .. PLL_BYPASS_FORCE = 0
// .. .. .. ==> 0XF8000100[4:4] = 0x00000000U
// .. .. .. ==> MASK : 0x00000010U VAL : 0x00000000U
// .. .. ..
EMIT_MASKWRITE(0XF8000100, 0x00000010U ,0x00000000U),
// .. .. .. FINISH: REMOVE PLL BY PASS
// .. .. .. SRCSEL = 0x0
// .. .. .. ==> 0XF8000120[5:4] = 0x00000000U
// .. .. .. ==> MASK : 0x00000030U VAL : 0x00000000U
// .. .. .. DIVISOR = 0x2
// .. .. .. ==> 0XF8000120[13:8] = 0x00000002U
// .. .. .. ==> MASK : 0x00003F00U VAL : 0x00000200U
// .. .. .. CPU_6OR4XCLKACT = 0x1
// .. .. .. ==> 0XF8000120[24:24] = 0x00000001U
// .. .. .. ==> MASK : 0x01000000U VAL : 0x01000000U
// .. .. .. CPU_3OR2XCLKACT = 0x1
// .. .. .. ==> 0XF8000120[25:25] = 0x00000001U
// .. .. .. ==> MASK : 0x02000000U VAL : 0x02000000U
// .. .. .. CPU_2XCLKACT = 0x1
// .. .. .. ==> 0XF8000120[26:26] = 0x00000001U
// .. .. .. ==> MASK : 0x04000000U VAL : 0x04000000U
// .. .. .. CPU_1XCLKACT = 0x1
// .. .. .. ==> 0XF8000120[27:27] = 0x00000001U
// .. .. .. ==> MASK : 0x08000000U VAL : 0x08000000U
// .. .. .. CPU_PERI_CLKACT = 0x1
// .. .. .. ==> 0XF8000120[28:28] = 0x00000001U
// .. .. .. ==> MASK : 0x10000000U VAL : 0x10000000U
// .. .. ..
EMIT_MASKWRITE(0XF8000120, 0x1F003F30U ,0x1F000200U),
// .. .. FINISH: ARM PLL INIT
// .. .. START: DDR PLL INIT
// .. .. PLL_RES = 0x2
// .. .. ==> 0XF8000114[7:4] = 0x00000002U
// .. .. ==> MASK : 0x000000F0U VAL : 0x00000020U
// .. .. PLL_CP = 0x2
// .. .. ==> 0XF8000114[11:8] = 0x00000002U
// .. .. ==> MASK : 0x00000F00U VAL : 0x00000200U
// .. .. LOCK_CNT = 0x12c
// .. .. ==> 0XF8000114[21:12] = 0x0000012CU
// .. .. ==> MASK : 0x003FF000U VAL : 0x0012C000U
// .. ..
EMIT_MASKWRITE(0XF8000114, 0x003FFFF0U ,0x0012C220U),
// .. .. .. START: UPDATE FB_DIV
// .. .. .. PLL_FDIV = 0x20
// .. .. .. ==> 0XF8000104[18:12] = 0x00000020U
// .. .. .. ==> MASK : 0x0007F000U VAL : 0x00020000U
// .. .. ..
EMIT_MASKWRITE(0XF8000104, 0x0007F000U ,0x00020000U),
// .. .. .. FINISH: UPDATE FB_DIV
// .. .. .. START: BY PASS PLL
// .. .. .. PLL_BYPASS_FORCE = 1
// .. .. .. ==> 0XF8000104[4:4] = 0x00000001U
// .. .. .. ==> MASK : 0x00000010U VAL : 0x00000010U
// .. .. ..
EMIT_MASKWRITE(0XF8000104, 0x00000010U ,0x00000010U),
// .. .. .. FINISH: BY PASS PLL
// .. .. .. START: ASSERT RESET
// .. .. .. PLL_RESET = 1
// .. .. .. ==> 0XF8000104[0:0] = 0x00000001U
// .. .. .. ==> MASK : 0x00000001U VAL : 0x00000001U
// .. .. ..
EMIT_MASKWRITE(0XF8000104, 0x00000001U ,0x00000001U),
// .. .. .. FINISH: ASSERT RESET
// .. .. .. START: DEASSERT RESET
// .. .. .. PLL_RESET = 0
// .. .. .. ==> 0XF8000104[0:0] = 0x00000000U
// .. .. .. ==> MASK : 0x00000001U VAL : 0x00000000U
// .. .. ..
EMIT_MASKWRITE(0XF8000104, 0x00000001U ,0x00000000U),
// .. .. .. FINISH: DEASSERT RESET
// .. .. .. START: CHECK PLL STATUS
// .. .. .. DDR_PLL_LOCK = 1
// .. .. .. ==> 0XF800010C[1:1] = 0x00000001U
// .. .. .. ==> MASK : 0x00000002U VAL : 0x00000002U
// .. .. ..
EMIT_MASKPOLL(0XF800010C, 0x00000002U),
// .. .. .. FINISH: CHECK PLL STATUS
// .. .. .. START: REMOVE PLL BY PASS
// .. .. .. PLL_BYPASS_FORCE = 0
// .. .. .. ==> 0XF8000104[4:4] = 0x00000000U
// .. .. .. ==> MASK : 0x00000010U VAL : 0x00000000U
// .. .. ..
EMIT_MASKWRITE(0XF8000104, 0x00000010U ,0x00000000U),
// .. .. .. FINISH: REMOVE PLL BY PASS
// .. .. .. DDR_3XCLKACT = 0x1
// .. .. .. ==> 0XF8000124[0:0] = 0x00000001U
// .. .. .. ==> MASK : 0x00000001U VAL : 0x00000001U
// .. .. .. DDR_2XCLKACT = 0x1
// .. .. .. ==> 0XF8000124[1:1] = 0x00000001U
// .. .. .. ==> MASK : 0x00000002U VAL : 0x00000002U
// .. .. .. DDR_3XCLK_DIVISOR = 0x2
// .. .. .. ==> 0XF8000124[25:20] = 0x00000002U
// .. .. .. ==> MASK : 0x03F00000U VAL : 0x00200000U
// .. .. .. DDR_2XCLK_DIVISOR = 0x3
// .. .. .. ==> 0XF8000124[31:26] = 0x00000003U
// .. .. .. ==> MASK : 0xFC000000U VAL : 0x0C000000U
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__synthesis_is_complete__ 0B
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axi4_sqrt_Pipeline_VITIS_LOOP_18_1.adb 118KB
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axi4_sqrt.bind.adb 94KB
axi4_sqrt_Pipeline_1.adb 93KB
axi4_sqrt_Pipeline_VITIS_LOOP_18_1.bind.adb 74KB
axi4_sqrt_Pipeline_3.bind.adb 69KB
axi4_sqrt_Pipeline_1.bind.adb 67KB
axi4_sqrt.sched.adb 64KB
axi4_sqrt_Pipeline_3.sched.adb 54KB
axi4_sqrt_Pipeline_1.sched.adb 53KB
axi4_sqrt_Pipeline_VITIS_LOOP_18_1.sched.adb 52KB
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solution1.aps 1KB
.automg_exit 32B
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runme.bat 229B
runme.bat 229B
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sim.bat 58B
sim.bat 58B
a.g.ld.2.m1.bc 16.96MB
a.g.ld.4.m2.bc 638KB
a.g.ld.5.gdce.bc 12KB
a.g.ld.3.fpc.bc 12KB
axi4_sqrt.g.bc 12KB
axi4_sqrt.bc 12KB
a.g.ld.0.bc 11KB
a.g.ld.1.lower.bc 11KB
a.o.3.bc 9KB
a.o.1.tmp.bc 5KB
a.o.2.bc 5KB
a.o.1.bc 5KB
a.g.1.bc 5KB
a.g.2.bc 5KB
a.g.2.prechk.bc 5KB
a.pp.bc 5KB
a.g.lto.bc 5KB
a.g.0.bc 5KB
a.g.bc 5KB
apatb_axi4_sqrt_ir.bc 3KB
design_1.bd 41KB
design_1.bda 5KB
design_1.bda 5KB
design_1.bit 3.86MB
design_1_wrapper.bit 3.86MB
design_1.bxml 3KB
ps7_init_gpl.c 313KB
ps7_init.c 312KB
xaxi4_sqrt.c 7KB
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axi4_sqrt_test.cpp_pre.cpp.tb.cpp 749KB
axi4_sqrt_test.cpp_pre.cpp 748KB
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design_1_xbar_0.cpp 179KB
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axi4_sqrt.cpp_pre.cpp.tb.cpp 94KB
axi4_sqrt.cpp_pre.cpp.tb.cpp 94KB
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