axi4stream_vip_axi4streampc.sv,systemverilog,xilinx_vip,D:/vivado/Vivado/2019.2/data/xilinx_vip/hdl/axi4stream_vip_axi4streampc.sv,incdir="$ref_dir/../../../../axi_dma_loop.srcs/sources_1/bd/design_1/ipshared/ec67/hdl"incdir="$ref_dir/../../../../axi_dma_loop.srcs/sources_1/bd/design_1/ipshared/0eaf/hdl"incdir="$ref_dir/../../../../axi_dma_loop.srcs/sources_1/bd/design_1/ipshared/1ddd/hdl/verilog"incdir="$ref_dir/../../../../axi_dma_loop.srcs/sources_1/bd/design_1/ipshared/b2d0/hdl/verilog"incdir="$ref_dir/../../../../axi_dma_loop.srcs/sources_1/bd/design_1/ipshared/8713/hdl"incdir="../../../../axi_dma_loop.srcs/sources_1/bd/design_1/ipshared/ec67/hdl"incdir="../../../../axi_dma_loop.srcs/sources_1/bd/design_1/ipshared/0eaf/hdl"incdir="../../../../axi_dma_loop.srcs/sources_1/bd/design_1/ip/design_1_zynq_ultra_ps_e_0_0/sim_tlm"incdir="../../../../axi_dma_loop.srcs/sources_1/bd/design_1/ip/design_1_zynq_ultra_ps_e_0_0"incdir="../../../../axi_dma_loop.srcs/sources_1/bd/design_1/ipshared/1ddd/hdl/verilog"incdir="../../../../axi_dma_loop.srcs/sources_1/bd/design_1/ipshared/b2d0/hdl/verilog"incdir="../../../../axi_dma_loop.srcs/sources_1/bd/design_1/ipshared/8713/hdl"
axi_vip_axi4pc.sv,systemverilog,xilinx_vip,D:/vivado/Vivado/2019.2/data/xilinx_vip/hdl/axi_vip_axi4pc.sv,incdir="$ref_dir/../../../../axi_dma_loop.srcs/sources_1/bd/design_1/ipshared/ec67/hdl"incdir="$ref_dir/../../../../axi_dma_loop.srcs/sources_1/bd/design_1/ipshared/0eaf/hdl"incdir="$ref_dir/../../../../axi_dma_loop.srcs/sources_1/bd/design_1/ipshared/1ddd/hdl/verilog"incdir="$ref_dir/../../../../axi_dma_loop.srcs/sources_1/bd/design_1/ipshared/b2d0/hdl/verilog"incdir="$ref_dir/../../../../axi_dma_loop.srcs/sources_1/bd/design_1/ipshared/8713/hdl"incdir="../../../../axi_dma_loop.srcs/sources_1/bd/design_1/ipshared/ec67/hdl"incdir="../../../../axi_dma_loop.srcs/sources_1/bd/design_1/ipshared/0eaf/hdl"incdir="../../../../axi_dma_loop.srcs/sources_1/bd/design_1/ip/design_1_zynq_ultra_ps_e_0_0/sim_tlm"incdir="../../../../axi_dma_loop.srcs/sources_1/bd/design_1/ip/design_1_zynq_ultra_ps_e_0_0"incdir="../../../../axi_dma_loop.srcs/sources_1/bd/design_1/ipshared/1ddd/hdl/verilog"incdir="../../../../axi_dma_loop.srcs/sources_1/bd/design_1/ipshared/b2d0/hdl/verilog"incdir="../../../../axi_dma_loop.srcs/sources_1/bd/design_1/ipshared/8713/hdl"
xil_common_vip_pkg.sv,systemverilog,xilinx_vip,D:/vivado/Vivado/2019.2/data/xilinx_vip/hdl/xil_common_vip_pkg.sv,incdir="$ref_dir/../../../../axi_dma_loop.srcs/sources_1/bd/design_1/ipshared/ec67/hdl"incdir="$ref_dir/../../../../axi_dma_loop.srcs/sources_1/bd/design_1/ipshared/0eaf/hdl"incdir="$ref_dir/../../../../axi_dma_loop.srcs/sources_1/bd/design_1/ipshared/1ddd/hdl/verilog"incdir="$ref_dir/../../../../axi_dma_loop.srcs/sources_1/bd/design_1/ipshared/b2d0/hdl/verilog"incdir="$ref_dir/../../../../axi_dma_loop.srcs/sources_1/bd/design_1/ipshared/8713/hdl"incdir="../../../../axi_dma_loop.srcs/sources_1/bd/design_1/ipshared/ec67/hdl"incdir="../../../../axi_dma_loop.srcs/sources_1/bd/design_1/ipshared/0eaf/hdl"incdir="../../../../axi_dma_loop.srcs/sources_1/bd/design_1/ip/design_1_zynq_ultra_ps_e_0_0/sim_tlm"incdir="../../../../axi_dma_loop.srcs/sources_1/bd/design_1/ip/design_1_zynq_ultra_ps_e_0_0"incdir="../../../../axi_dma_loop.srcs/sources_1/bd/design_1/ipshared/1ddd/hdl/verilog"incdir="../../../../axi_dma_loop.srcs/sources_1/bd/design_1/ipshared/b2d0/hdl/verilog"incdir="../../../../axi_dma_loop.srcs/sources_1/bd/design_1/ipshared/8713/hdl"
axi4stream_vip_pkg.sv,systemverilog,xilinx_vip,D:/vivado/Vivado/2019.2/data/xilinx_vip/hdl/axi4stream_vip_pkg.sv,incdir="$ref_dir/../../../../axi_dma_loop.srcs/sources_1/bd/design_1/ipshared/ec67/hdl"incdir="$ref_dir/../../../../axi_dma_loop.srcs/sources_1/bd/design_1/ipshared/0eaf/hdl"incdir="$ref_dir/../../../../axi_dma_loop.srcs/sources_1/bd/design_1/ipshared/1ddd/hdl/verilog"incdir="$ref_dir/../../../../axi_dma_loop.srcs/sources_1/bd/design_1/ipshared/b2d0/hdl/verilog"incdir="$ref_dir/../../../../axi_dma_loop.srcs/sources_1/bd/design_1/ipshared/8713/hdl"incdir="../../../../axi_dma_loop.srcs/sources_1/bd/design_1/ipshared/ec67/hdl"incdir="../../../../axi_dma_loop.srcs/sources_1/bd/design_1/ipshared/0eaf/hdl"incdir="../../../../axi_dma_loop.srcs/sources_1/bd/design_1/ip/design_1_zynq_ultra_ps_e_0_0/sim_tlm"incdir="../../../../axi_dma_loop.srcs/sources_1/bd/design_1/ip/design_1_zynq_ultra_ps_e_0_0"incdir="../../../../axi_dma_loop.srcs/sources_1/bd/design_1/ipshared/1ddd/hdl/verilog"incdir="../../../../axi_dma_loop.srcs/sources_1/bd/design_1/ipshared/b2d0/hdl/verilog"incdir="../../../../axi_dma_loop.srcs/sources_1/bd/design_1/ipshared/8713/hdl"
axi_vip_pkg.sv,systemverilog,xilinx_vip,D:/vivado/Vivado/2019.2/data/xilinx_vip/hdl/axi_vip_pkg.sv,incdir="$ref_dir/../../../../axi_dma_loop.srcs/sources_1/bd/design_1/ipshared/ec67/hdl"incdir="$ref_dir/../../../../axi_dma_loop.srcs/sources_1/bd/design_1/ipshared/0eaf/hdl"incdir="$ref_dir/../../../../axi_dma_loop.srcs/sources_1/bd/design_1/ipshared/1ddd/hdl/verilog"incdir="$ref_dir/../../../../axi_dma_loop.srcs/sources_1/bd/design_1/ipshared/b2d0/hdl/verilog"incdir="$ref_dir/../../../../axi_dma_loop.srcs/sources_1/bd/design_1/ipshared/8713/hdl"incdir="../../../../axi_dma_loop.srcs/sources_1/bd/design_1/ipshared/ec67/hdl"incdir="../../../../axi_dma_loop.srcs/sources_1/bd/design_1/ipshared/0eaf/hdl"incdir="../../../../axi_dma_loop.srcs/sources_1/bd/design_1/ip/design_1_zynq_ultra_ps_e_0_0/sim_tlm"incdir="../../../../axi_dma_loop.srcs/sources_1/bd/design_1/ip/design_1_zynq_ultra_ps_e_0_0"incdir="../../../../axi_dma_loop.srcs/sources_1/bd/design_1/ipshared/1ddd/hdl/verilog"incdir="../../../../axi_dma_loop.srcs/sources_1/bd/design_1/ipshared/b2d0/hdl/verilog"incdir="../../../../axi_dma_loop.srcs/sources_1/bd/design_1/ipshared/8713/hdl"
axi4stream_vip_if.sv,systemverilog,xilinx_vip,D:/vivado/Vivado/2019.2/data/xilinx_vip/hdl/axi4stream_vip_if.sv,incdir="$ref_dir/../../../../axi_dma_loop.srcs/sources_1/bd/design_1/ipshared/ec67/hdl"incdir="$ref_dir/../../../../axi_dma_loop.srcs/sources_1/bd/design_1/ipshared/0eaf/hdl"incdir="$ref_dir/../../../../axi_dma_loop.srcs/sources_1/bd/design_1/ipshared/1ddd/hdl/verilog"incdir="$ref_dir/../../../../axi_dma_loop.srcs/sources_1/bd/design_1/ipshared/b2d0/hdl/verilog"incdir="$ref_dir/../../../../axi_dma_loop.srcs/sources_1/bd/design_1/ipshared/8713/hdl"incdir="../../../../axi_dma_loop.srcs/sources_1/bd/design_1/ipshared/ec67/hdl"incdir="../../../../axi_dma_loop.srcs/sources_1/bd/design_1/ipshared/0eaf/hdl"incdir="../../../../axi_dma_loop.srcs/sources_1/bd/design_1/ip/design_1_zynq_ultra_ps_e_0_0/sim_tlm"incdir="../../../../axi_dma_loop.srcs/sources_1/bd/design_1/ip/design_1_zynq_ultra_ps_e_0_0"incdir="../../../../axi_dma_loop.srcs/sources_1/bd/design_1/ipshared/1ddd/hdl/verilog"incdir="../../../../axi_dma_loop.srcs/sources_1/bd/design_1/ipshared/b2d0/hdl/verilog"incdir="../../../../axi_dma_loop.srcs/sources_1/bd/design_1/ipshared/8713/hdl"
axi_vip_if.sv,systemverilog,xilinx_vip,D:/vivado/Vivado/2019.2/data/xilinx_vip/hdl/axi_vip_if.sv,incdir="$ref_dir/../../../../axi_dma_loop.srcs/sources_1/bd/design_1/ipshared/ec67/hdl"incdir="$ref_dir/../../../../axi_dma_loop.srcs/sources_1/bd/design_1/ipshared/0eaf/hdl"incdir="$ref_dir/../../../../axi_dma_loop.srcs/sources_1/bd/design_1/ipshared/1ddd/hdl/verilog"incdir="$ref_dir/../../../../axi_dma_loop.srcs/sources_1/bd/design_1/ipshared/b2d0/hdl/verilog"incdir="$ref_dir/../../../../axi_dma_loop.srcs/sources_1/bd/design_1/ipshared/8713/hdl"incdir="../../../../axi_dma_loop.srcs/sources_1/bd/design_1/ipshared/ec67/hdl"incdir="../../../../axi_dma_loop.srcs/sources_1/bd/design_1/ipshared/0eaf/hdl"incdir="../../../../axi_dma_loop.srcs/sources_1/bd/design_1/ip/design_1_zynq_ultra_ps_e_0_0/sim_tlm"incdir="../../../../axi_dma_loop.srcs/sources_1/bd/design_1/ip/design_1_zynq_ultra_ps_e_0_0"incdir="../../../../axi_dma_loop.srcs/sources_1/bd/design_1/ipshared/1ddd/hdl/verilog"incdir="../../../../axi_dma_loop.srcs/sou
没有合适的资源?快使用搜索试试~ 我知道了~
FPGA MPSoC_XCZU2EG实现AXI DMA环路测试(VITIS实现).zip
共2000个文件
h:814个
c:410个
o:245个
1.该资源内容由用户上传,如若侵权请联系客服进行举报
2.虚拟产品一经售出概不退款(资源遇到问题,请及时私信上传者)
2.虚拟产品一经售出概不退款(资源遇到问题,请及时私信上传者)
版权申诉
0 下载量 126 浏览量
2023-04-26
18:55:18
上传
评论
收藏 83.57MB ZIP 举报
温馨提示
FPGA MPSoC XCZU2CG、XCZU2EG和XCZU4EV驱动程序。 基于VITIS实现。 项目代码可顺利编译运行~
资源推荐
资源详情
资源评论
收起资源包目录
FPGA MPSoC_XCZU2EG实现AXI DMA环路测试(VITIS实现).zip (2000个子文件)
30266643b54d001c1a12db4a59112dfb 9KB
30d64167b54d001c1a12db4a59112dfb 1KB
60966e68b54d001c1a12db4a59112dfb 1KB
7037162eb54d001c1a12db4a59112dfb 9KB
70ca1d2c134d001c120dd332559ba12c 9KB
80f58667b54d001c1a12db4a59112dfb 1KB
90c29567b54d001c1a12db4a59112dfb 1KB
__synthesis_is_complete__ 0B
libxil.a 4.72MB
libxil.a 3.84MB
libxil.a 2.28MB
libxil.a 2.28MB
libgcc.a 1.73MB
libc.a 1.02MB
libxilsecure.a 587KB
libxilsecure.a 586KB
libxilskey.a 576KB
libm.a 576KB
libxilpm.a 573KB
libxilfpga.a 295KB
libxilffs.a 48KB
libgloss.a 22KB
a04f0867b54d001c1a12db4a59112dfb 1KB
a0bdcd51b54d001c1a12db4a59112dfb 9KB
.analytics 1KB
assumedExternalFilesCache 4B
runme.bat 229B
runme.bat 229B
bd_afc3.bd 107KB
bd_afc3.bd 107KB
design_1.bd 26KB
design_1_wrapper.bif 225B
design_1_wrapper.bit 5.31MB
design_1_wrapper.bit 5.31MB
design_1_wrapper.bit 5.31MB
design_1_wrapper.bit 5.31MB
design_1_wrapper.bit 5.31MB
design_1_wrapper.bit 5.31MB
bd_afc3.bxml 13KB
design_1.bxml 6KB
ffunicode.c 1.87MB
psu_init.c 633KB
psu_init.c 633KB
psu_init.c 633KB
psu_init.c 633KB
psu_init.c 633KB
psu_init_gpl.c 632KB
psu_init_gpl.c 632KB
psu_init_gpl.c 632KB
psu_init_gpl.c 632KB
ff.c 223KB
xfsbl_ddr_init.c 214KB
xilskey_eps_zynqmp.c 102KB
xilfpga_pcap.c 75KB
pm_clock.c 70KB
xsysmonpsu.c 69KB
xsysmonpsu.c 69KB
xsysmonpsu.c 69KB
pm_api_sys.c 64KB
xaxipmon.c 63KB
xaxipmon.c 63KB
xaxipmon.c 63KB
pm_core.c 60KB
pm_ddr.c 58KB
xfsbl_initialization.c 56KB
xfsbl_partition_load.c 52KB
xaxidma_bdring.c 52KB
xaxidma_bdring.c 52KB
xaxidma_bdring.c 52KB
pm_reset.c 49KB
xsecure.c 48KB
xsecure.c 48KB
xsecure_aes.c 46KB
xsecure_aes.c 46KB
xilskey_utils.c 43KB
xzdma.c 41KB
xzdma.c 41KB
xzdma.c 41KB
xresetps.c 40KB
xresetps.c 40KB
xresetps.c 40KB
xfsbl_qspi.c 40KB
xscugic.c 38KB
xscugic.c 38KB
xilskey_eps_zynqmp_puf.c 37KB
xclockps_mux.c 35KB
xclockps_mux.c 35KB
xclockps_mux.c 35KB
pm_power.c 34KB
xfsbl_plpartition_valid.c 33KB
xfsbl_handoff.c 32KB
xcsudma.c 32KB
xcsudma.c 32KB
xcsudma.c 32KB
pm_cfg_obj.c 31KB
pm_pinctrl.c 30KB
pm_periph.c 30KB
pm_master.c 29KB
xgpiops.c 28KB
xgpiops.c 28KB
共 2000 条
- 1
- 2
- 3
- 4
- 5
- 6
- 20
资源评论
不脱发的程序猿
- 粉丝: 24w+
- 资源: 5804
上传资源 快速赚钱
- 我的内容管理 展开
- 我的资源 快来上传第一个资源
- 我的收益 登录查看自己的收益
- 我的积分 登录查看自己的积分
- 我的C币 登录后查看C币余额
- 我的收藏
- 我的下载
- 下载帮助
安全验证
文档复制为VIP权益,开通VIP直接复制
信息提交成功