本人声明，这是我们上学期的课程设计内容，完全出自本人之手
模块一：
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity display is
port(din0:in std_logic_vector(3 downto 0);
din1:in std_logic_vector(3 downto 0);
din2:in std_logic_vector(3 downto 0);
din3:in std_logic_vector(3 downto 0);
din4:in std_logic_vector(3 downto 0);
din5:in std_logic_vector(3 downto 0);
clk:in std_logic;
led_sa: out std_logic;
led_sb: out std_logic;
led_sc: out std_logic;
led_a: out std_logic;
led_b: out std_logic;
led_c: out std_logic;
led_d: out std_logic;
led_e: out std_logic;
led_f: out std_logic;
led_g: out std_logic;
led_dp: out std_logic);
end display;
architecture behav of display is
signal seg:std_logic_vector(6 downto 0);
signal sel:std_logic_vector(2 downto 0);
signal num:std_logic_vector(3 downto 0);
signal s:std_logic_vector(2 downto 0);
begin
led_sa<=sel(0);
led_sb<=sel(1);
led_sc<=sel(2);
led_a<=seg(0);
led_b<=seg(1);
led_c<=seg(2);
led_d<=seg(3);
led_e<=seg(4);
led_f<=seg(5);
led_g<=seg(6);
process(clk)
begin
if clk'event and clk='1'then
if s="101" then
s<="000";
else
s<=s+'1';
end if;
end if;
end process;
process(s,din0,din1,din2,din3,din4,din5)
begin
