function sel_trans_ctrl_config(this_block)
% Revision History:
%
% 30-Jan-2022 (20:19 hours):
% Original code was machine generated by Xilinx's System Generator after parsing
% D:\Matlab\sel_trans.vhd
%
%
this_block.setTopLevelLanguage('VHDL');
this_block.setEntityName('sel_trans_ctrl');
% System Generator has to assume that your entity has a combinational feed through;
% if it doesn't, then comment out the following line:
this_block.tagAsCombinational;
this_block.addSimulinkInport('rst');
this_block.addSimulinkInport('out_sel');
this_block.addSimulinkInport('dma_en');
this_block.addSimulinkInport('iq');
this_block.addSimulinkInport('iq_count');
this_block.addSimulinkInport('iq_len');
this_block.addSimulinkInport('spect');
this_block.addSimulinkInport('spect_count');
this_block.addSimulinkInport('spect_len');
this_block.addSimulinkInport('ready_in');
this_block.addSimulinkInport('ddc_index');
this_block.addSimulinkInport('time_count');
this_block.addSimulinkInport('date');
this_block.addSimulinkOutport('iq_re');
this_block.addSimulinkOutport('spect_re');
this_block.addSimulinkOutport('ready_out');
this_block.addSimulinkOutport('data');
this_block.addSimulinkOutport('valid');
this_block.addSimulinkOutport('last');
this_block.addSimulinkOutport('keep');
this_block.addSimulinkOutport('trans_status');
iq_re_port = this_block.port('iq_re');
iq_re_port.setType('Bool');
iq_re_port.useHDLVector(false);
spect_re_port = this_block.port('spect_re');
spect_re_port.setType('Bool');
spect_re_port.useHDLVector(false);
ready_out_port = this_block.port('ready_out');
ready_out_port.setType('Bool');
ready_out_port.useHDLVector(false);
data_port = this_block.port('data');
data_port.setType('UFix_32_0');
valid_port = this_block.port('valid');
valid_port.setType('Bool');
valid_port.useHDLVector(false);
last_port = this_block.port('last');
last_port.setType('Bool');
last_port.useHDLVector(false);
keep_port = this_block.port('keep');
keep_port.setType('UFix_4_0');
head_ct_port = this_block.port('trans_status');
head_ct_port.setType('UFix_3_0');
% -----------------------------
if (this_block.inputTypesKnown)
% do input type checking, dynamic output type and generic setup in this code block.
if (this_block.port('rst').width ~= 1);
this_block.setError('Input data type for port "rst" must have width=1.');
end
this_block.port('rst').useHDLVector(false);
if (this_block.port('out_sel').width ~= 1);
this_block.setError('Input data type for port "out_sel" must have width=1.');
end
this_block.port('out_sel').useHDLVector(false);
if (this_block.port('dma_en').width ~= 1);
this_block.setError('Input data type for port "dma_en" must have width=1.');
end
this_block.port('dma_en').useHDLVector(false);
if (this_block.port('iq').width ~= 32);
this_block.setError('Input data type for port "iq" must have width=32.');
end
if (this_block.port('iq_count').width ~= 16);
this_block.setError('Input data type for port "iq_count" must have width=16.');
end
if (this_block.port('iq_len').width ~= 16);
this_block.setError('Input data type for port "iq_len" must have width=16.');
end
if (this_block.port('spect').width ~= 32);
this_block.setError('Input data type for port "spect" must have width=32.');
end
if (this_block.port('spect_count').width ~= 16);
this_block.setError('Input data type for port "spect_count" must have width=16.');
end
if (this_block.port('spect_len').width ~= 16);
this_block.setError('Input data type for port "spect_len" must have width=16.');
end
if (this_block.port('ready_in').width ~= 1);
this_block.setError('Input data type for port "ready_in" must have width=1.');
end
this_block.port('ready_in').useHDLVector(false);
if (this_block.port('ddc_index').width ~= 3);
this_block.setError('Input data type for port "ddc_index" must have width=3.');
end
if (this_block.port('time_count').width ~= 32);
this_block.setError('Input data type for port "time_count" must have width=32.');
end
if (this_block.port('date').width ~= 32);
this_block.setError('Input data type for port "date" must have width=32.');
end
end % if(inputTypesKnown)
% -----------------------------
% -----------------------------
if (this_block.inputRatesKnown)
setup_as_single_rate(this_block,'clk','ce')
end % if(inputRatesKnown)
% -----------------------------
uniqueInputRates = unique(this_block.getInputRates);
% Add addtional source files as needed.
% |-------------
% | Add files in the order in which they should be compiled.
% | If two files "a.vhd" and "b.vhd" contain the entities
% | entity_a and entity_b, and entity_a contains a
% | component of type entity_b, the correct sequence of
% | addFile() calls would be:
% | this_block.addFile('b.vhd');
% | this_block.addFile('a.vhd');
% |-------------
% this_block.addFile('');
% this_block.addFile('');
this_block.addFile('sel_trans.vhd');
return;
% ------------------------------------------------------------
function setup_as_single_rate(block,clkname,cename)
inputRates = block.inputRates;
uniqueInputRates = unique(inputRates);
if (length(uniqueInputRates)==1 & uniqueInputRates(1)==Inf)
block.addError('The inputs to this block cannot all be constant.');
return;
end
if (uniqueInputRates(end) == Inf)
hasConstantInput = true;
uniqueInputRates = uniqueInputRates(1:end-1);
end
if (length(uniqueInputRates) ~= 1)
block.addError('The inputs to this block must run at a single rate.');
return;
end
theInputRate = uniqueInputRates(1);
for i = 1:block.numSimulinkOutports
block.outport(i).setRate(theInputRate);
end
block.addClkCEPair(clkname,cename,theInputRate);
return;
% ------------------------------------------------------------
