Clock Regions-Block Scope:
+--------------------------------------------------------------------------+
| (X0,Y*): (Xmin,Xmax,Ymin,Ymax) | (X1,Y*): (Xmin,Xmax,Ymin,Ymax)
+--------------------------------------------------------------------------+
| (X0,Y2): (0,39,60,89) | (X1,Y2): (40,75,60,89)
| (X0,Y1): (0,39,30,59) | (X1,Y1): (40,75,30,59)
| (X0,Y0): (0,39,0,29) | (X1,Y0): (40,75,0,29)
+--------------------------------------------------------------------------+
Clock Regions-Clock Primitives:
+--------------------------------------------------------------------------------------------------------------------------------------+
| Clock Region Name | CLK PAD | PLL PAD | RCKB | IOCKGATE | IOCKDIV | CLMA | CLMS | DRM | APM
+--------------------------------------------------------------------------------------------------------------------------------------+
| (X0,Y0) | 4 | 6 | 4 | 2 | 2 | 520 | 180 | 12 | 0
| (X0,Y1) | 4 | 6 | 4 | 2 | 2 | 610 | 210 | 12 | 0
| (X0,Y2) | 4 | 6 | 4 | 2 | 2 | 524 | 180 | 6 | 0
| (X1,Y0) | 4 | 6 | 4 | 2 | 2 | 450 | 150 | 6 | 10
| (X1,Y1) | 4 | 6 | 4 | 2 | 2 | 540 | 180 | 6 | 10
| (X1,Y2) | 4 | 6 | 4 | 2 | 2 | 630 | 210 | 6 | 10
+--------------------------------------------------------------------------------------------------------------------------------------+
Global Clock Buffer Constraint Details:
+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
| Source Name | Source Pin | Source-Buffer Net | Buffer Input Pin | Buffer Name | Buffer Output Pin | Buffer-Load Net | Clock Region Of Buffer Site | Buffer Site | IO Load Clock Region | Non-IO Load Clock Region | Clock Loads | Non-Clock Loads
+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
| sys_clk_ibuf/opit_1 | INCK | _N0 | CLK | clkbufg_0/gopclkbufg | CLKOUT | ntclkbufg_0 | --- | --- | --- | --- | 60 | 0
+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
Global Clock Source Constraint Details:
+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
| Source Name | Source Pin | Source-Load Net | Clock Region Of Source Site | Source Site | Clock Buffer Loads | Non-Clock Buffer Loads
+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
| sys_clk_ibuf/opit_1 | INCK | _N0 | (X0,Y2) | IOL_7_298 | 1 | 0
+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
Device Cell Placement Summary for Global Clock Buffer:
+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
| Source Name | Source Pin | Source-Buffer Net | Buffer Input Pin | Buffer Name | Buffer Output Pin | Buffer-Load Net | Buffer Site | IO Load Clock Region | Non-IO Load Clock Region | Clock Loads | Non-Clock Loads
+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
| sys_clk_ibuf/opit_1 | INCK | _N0 | CLK | clkbufg_0/gopclkbufg | CLKOUT | ntclkbufg_0 | USCM_74_104 | --- | (50,71,45,56) | 60 | 0
+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
Device Cell Placement Summary for Global Clock Source:
+------------------------------------------------------------------------------------------------------------------------------------------+
| Source Name | Source Pin | Source-Load Net | Source Site | Clock Buffer Loads | Non-Clock Buffer Loads
+------------------------------------------------------------------------------------------------------------------------------------------+
| sys_clk_ibuf/opit_1 | INCK | _N0 | IOL_7_298 | 1 | 0
+------------------------------------------------------------------------------------------------------------------------------------------+
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FPGA PGL22G制作交通灯【Verilog HDL驱动】.zip
共347个文件
log:89个
qdb:58个
_info:29个
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FPGA PGL22G驱动程序,Verilog HDL实现。 项目代码可顺利编译运行~
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FPGA PGL22G制作交通灯【Verilog HDL驱动】.zip (347个子文件)
_info 216KB
_info 170KB
_info 145KB
_info 97KB
_info 95KB
_info 94KB
_info 74KB
_info 61KB
_info 46KB
_info 39KB
_info 29KB
_info 27KB
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_info 9KB
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_info 2KB
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_info 1KB
_info 1KB
_info 1KB
_info 1KB
_info 741B
_vmake 29B
_vmake 29B
_vmake 29B
_vmake 29B
_vmake 29B
_vmake 29B
_vmake 29B
_vmake 29B
_vmake 29B
_vmake 29B
_vmake 29B
_vmake 29B
_vmake 29B
_vmake 29B
_vmake 29B
_vmake 29B
_vmake 29B
_vmake 29B
_vmake 29B
_vmake 29B
_vmake 29B
_vmake 29B
_vmake 29B
_vmake 29B
_vmake 29B
_vmake 29B
_vmake 29B
_vmake 29B
_vmake 29B
top_traffic_pnr.adf 118KB
top_traffic_plc.adf 48KB
top_traffic_plc.adf 48KB
top_traffic_syn.adf 43KB
top_traffic_map.adf 42KB
top_traffic_comp.adf 33KB
top_traffic_rtp.adf 3KB
run_post_syn.bat 340B
run_behav.bat 331B
run_sim.bat 65B
top_traffic.bgr 2KB
top_traffic.bgr 2KB
top_traffic.ccr 2KB
top_traffic.cmr 1KB
top_traffic.cmr 1KB
rtr.db 294KB
rtr.db 288KB
snr.db 222KB
snr.db 221KB
dmr.db 100KB
dmr.db 100KB
prr.db 98KB
prr.db 98KB
bgr.db 11KB
bgr.db 11KB
cmr.db 9KB
cmr.db 9KB
top_traffic.dmr 22KB
top_traffic.dmr 22KB
top_traffic_2022_09_24_14_38_50.fdc 8KB
top_traffic_2022_08_22_18_40_11.fdc 8KB
top_traffic_2022_08_22_19_34_25.fdc 8KB
top_traffic_2022_08_22_19_35_14.fdc 8KB
top_traffic_2022_08_20_14_20_11.fdc 7KB
top_traffic.fdc 7KB
modelsim.ini 93KB
modelsim.ini 92KB
modelsim.ini 92KB
run_2022-09-24-14-45-58.log 207KB
run_2022-08-22-19-35-45.log 133KB
run_2022-10-08-09-50-57.log 129KB
run_2022-08-22-18-53-57.log 69KB
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